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visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2010 pc8641 and pc8641d power architecture integrated processor datasheet - preliminary specification features ? dual-e600 power architecture? processor cores ? pd typically 23.9w at 1.25 ghz (v dd = 1.05v) ; 32.1w at 1.5 ghz (v dd = 1.1v) ? selectable mpx bus up to 600mhz (64 bits) ? integrated l1: 32 kb instruction and 32 kb data cache (per core with parity protection) ? integrated l2: 1 mb per core with optional ecc ? serial rapidio interface 1x, 4x (1.25, 2.5 and 3.125gbaud) ? pci express interface 1x, 4x or 8x (2.5gbaud/lane) ? ethernet interface : four 10 /100/1000 ethernet controllers ? memory controller : support dual 64-bit ddr and ddrii with up to 600 mhz data rate with ecc ? up to 16gb per memory controller. ? dma controller : four independent channels with bandwith control per channel ? f int max = 1500 mhz ? f bus max = 600 mhz overview the pc8641 processor family integrates either one or two po wer architecture e600 processor cores with system logic required for networking, storage, wireless infrastructure, and general-purpose embedded applications. the pc8641 inte- grates one e600 core while the pc8641d integrates two cores. this section provides a high-level over view of the pc8641 and pc8641d features. when referring to the pc8641 through- out the document, the functionality described applies to both t he pc8641 and the pc8641d. any differences specific to the pc8641d are noted. figure 1-1 on page 2 shows the major functional units within the pc8641 and pc8641d. the major difference between the pc8641 and pc8641d is that there are two cores on the pc8641d. screening ? full military temperature range (t c = -55 c, t j = +125 c) ? industrial temperature range (t c = -40 c, t j = +110 c) 0893c?hirel?01/10
2 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 1. block diagram figure 1-1. pc8641 and pc8641d and 1x/4x srio (2.5 gb/s)] [x1/x2/x4/x8 pci exp (4 gb/s) or [2-x1/x2/x4/x8 pci express (8 gb/s)] multiprocessor sdram irqs external control (mpic) sdram rom, gpio dual universal asynchronous receiver/transmitter (duart) serial enhanced tsec controller 10/100/1gb pci express interface ocean switch fabric mpx coherency module (mcm) platform mpx bus platform bus programmable interrupt controller rmii, gmii, mii, rgmii, tbi, rtbi rmii, gmii, mii, rgmii, tbi, rtbi rmii, gmii, mii, rgmii, tbi, rtbi rmii, gmii, mii, rgmii, tbi, rtbi serial rapidio interface or pci express interface four-channel dma controller i 2 c controller i 2 c controller local bus controller (lbc) ddr sdram controller ddr sdram controller enhanced tsec controller 10/100/1gb enhanced tsec controller 10/100/1gb enhanced tsec controller 10/100/1gb i 2 c i 2 c 32-kbyte l1 instruction cache e600 core e600 core block 1-mbyte l2 cache l1 data cache 32-kbyte 32-kbyte l1 instruction cache e600 core e600 core block 1-mbyte l2 cache l1 data cache 32-kbyte
3 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 2. key features the following lists an overview of the pc8641 key feature set: ? major features of the e600 core are as follows: ? high-performance, 32-bit superscalar microprocessor that implements the power architecture ? eleven independent execution units and three register files ? branch processing unit (bpu) ? four integer units (ius) that share 32 gprs for integer operands ? 64-bit floating-point unit (fpu) ? four vector units and a 32-entry vector register file (vrs) ? three-stage load/store unit (lsu) ? three issue queues, fiq, viq, and giq, can accept as many as one, two, and three instructions, respectively, in a cycle. ? rename buffers ? dispatch unit ? completion unit ? two separate 32-kbyte instruction and data level 1 (l1) caches ? integrated 1-mbyte, eight-way set-associative unified instruction and data level 2 (l2) cache with ecc ? 36-bit real addressing ? separate memory management units (mmus) for instructions and data ? multiprocessing support features ? power and thermal management ? performance monitor ? in-system testability and debugging features ? reliability and serviceability ? mpx coherency module (mcm) ? ten local address windows plus two default windows ? optional low memory offset mode for core 1 to allow for address disambiguation ? address translation and mapping units (atmus) ? eight local access windows define mapping within local 36-bit address space ? inbound and outbound atmus map to larger external address spaces ? three inbound windows plus a co nfiguration window on pci express ? four inbound windows plus a default window on serial rapidio ? four outbound windows plus default translation for pci express ? eight outbound windows plus default translat ion for serial rapidio with segmentation and sub-segmentation support ? ddr memory controllers ? dual 64-bit memory cont rollers (72-bit with ecc) ? support of up to a 333-mhz clock rate and a 667-mhz ddr2 sdram ? support for ddr, ddr2 sdram
4 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 ? up to 16 gbytes per memory controller ? cache line and page interleaving between memory controllers. ? serial rapidio interface unit ? supports rapidio interconnect specification, revision 1.2 ? both 1x and 4x lp-serial link interfaces ? transmission rates of 1.25-, 2.5-, and 3.125-gbaud (data rates of 1.0-, 2.0-, and 2.5-gbps) per lane ? rapidio?compliant message unit ? rapidio atomic transactions to the memory controller ? pci express interface ? pci express 1.0a compatible ? supports x1, x2, x4, and x8 link widths ? 2.5 gbaud, 2.0 gbps lane ? four enhanced three-speed ethernet controllers (etsecs) ? three-speed support (10/100/1000 mbps) ? four ieee ? 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers ? support of the following physical interfaces: mii, rmii, gmii, rgmii, tbi, and rtbi ? support a full-duplex fifo mode for high-efficiency asic connectivity ? tcp/ip off-load ? header parsing ? quality of service support ? vlan insertion and deletion ? mac address recognition ? buffer descriptors are backward compatible with powerquicc ii and powerquicc iii programming models ? rmon statistics support ? mii management interface for control and status ? programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture ? supports 16 programmable interrupt and processor task priority levels ? supports 12 discrete external interrupts and 48 internal interrupts ? eight global high resolution timers/counters that can generate interrupts ? allows processors to interrupt each other with 32b messages ? support for pci-express message-shared interrupts (msis) ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 166 mhz ? eight chip selects support eight external slaves ? integrated dma controller ? four-channel controller ? all channels accessible by both the local and the remote masters
5 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] ? supports transfers to or from any local memory or i/o port ? ability to start and flow control each dm a channel from extern al 3-pin interface ? device performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-spe cific events ? supports 64 reference events that can be counted on any of the 8 counters ? supports duration and quantity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and ch aining capability ? ability to generate an interrupt on overflow ?dual i 2 c controllers ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? boot sequencer ? optionally loads configuration data from serial rom at reset via the i 2 c interface ? can be used to initialize configuration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc ?duart ? two 4-wire interfaces (sin, sout, rts , cts ) ? programming model compatible with the original 16450 uart and the pc16550d ? ieee 1149.1-compliant, jtag boundary scan ? available as 1023 pin hi-cte flip chip ceramic land grid (fc-clga) and ceramic ball grid array (fc- cbga) 3. electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the pc8641. the pc8641 is currently ta rgeted to these specifications. 3.1 overall dc electr ical characteristics this section covers the ratings, conditions, and other characteristics.
6 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 3.1.1 absolute maximum ratings table 3-1 provides the absolute maximum ratings. notes: 1. functional and tested operating conditions are given in table 3-2 on page 7 . absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. core 1 characteristics apply only to pc8641d. if two separate power supplies are used for v dd _core0 and v dd _core1, they must be kept within 100 mv of each other during normal run time. 3. the -0.3 to 2.75v range is for ddr and -0.3 to 1.98v range is for ddr2. 4. the 3.63v maximum is only supported when the port is confi gured in gmii, mii, rmii, or tbi modes; otherwise the 2.75v maximum applies. see section 9.2 ?fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications? on page 27 for details on the recommended oper ating conditions per protocol. 5. during run time (m,l,t,o)v in and d n _mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 3-1 on page 8 . table 3-1. absolute maximum ratings (1) characteristic symbol maximum value unit notes cores supply voltages v dd _core0 v dd _core1 -0.3 to 1.21 v v (2) cores pll supply av dd _core0 av dd _core1 -0.3 to 1.21 v v serdes transceiver supply (ports 1 and 2) sv dd -0.3 to 1.21 v v serdes serial i/o supply port 1 xv dd _ srds1 -0.3 to 1.21 v v serdes serial i/o supply port 2 xv dd _ srds2 -0.3 to 1.21 v v serdes dll and pll supply voltage for port 1 and port 2 av dd _srds1 av dd _srds2 -0.3 to 1.21 v v platform supply voltage v dd _plat -0.3 to 1.21 v v local bus and platform pll supply voltage av dd _lb av dd _plat -0.3 to 1.21 v v ddr and ddr2 sdram i/o supply voltages d1_gv dd d2_gv dd -0.3 to 2.75 v v (3) -0.3 to 1.98 v v (3) etsec 1 and 2 i/o supply voltage lv dd -0.3 to 3.63 v v (4) -0.3 to 2.75 v v (4) etsec 3 and 4 i/o supply voltage tv dd -0.3 to 3.63 v v (4) -0.3 to 2.75 v v (4) local bus, duart, dma, multiprocessor interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, jtag and miscellaneous i/o voltage ov dd -0.3 to 3.63 v v input voltage ddr and ddr2 sdram signals dn_mv in -0.3 to (dn_gv dd + 0.3) v (5) ddr and ddr2 sdram reference dn_mv ref -0.3 to (dn_gv dd /2 + 0.3) v three-speed ethernet signals lv in tv in gnd to (lv dd + 0.3) gnd to (tv dd + 0.3) v (5) duart, local bus, dma, multiprocessor interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, jtag and miscellaneous i/o voltage ov in gnd to (0v dd + 0.3) v (5) storage temperature range t stg -55 to 150 c
7 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 3.1.2 recommended operating conditions table 3-2 provides the recommended operating conditions for the pc8641. note that the values in table 3-2 are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. for details on order in formation and specific operating conditions for parts, see section 22. ?ordering information? on page 106 .? notes: 1. core 1 characteristics apply only to pc8641d. table 3-2. recommended operating conditions characteristic symbol recommended value unit notes cores supply voltages v dd _core0 v dd _core1 1.10 50 mv v (1)(2)(8) 1.05 50 mv (1)(2)(7) cores pll supply av dd _core0 av dd _core1 1.10 50 mv v (8) 1.05 50 mv (7) serdes transceiver supply (ports 1 and 2) sv dd 1.10 50 mv v (8)(11) 1.05 50 mv (7)(11) serdes serial i/o supply port 1 xv dd _srds1 1.10 50 mv v (8) 1.05 50 mv (7) serdes serial i/o supply port 2 xv dd _srds2 1.10 50 mv v (8) 1.05 50 mv (7) serdes dll and pll supply voltage for port 1 and port 2 av dd _srds1 av dd _srds2 1.10 50 mv v (8) 1.05 50 mv (7) platform supply voltage v dd _plat 1.10 50 mv v (8) 1.05 50 mv (7) local bus and platform pll supply voltage av dd _lb av dd _plat 1.10 50 mv v (8) 1.05 50 mv (7) ddr and ddr2 sdram i/o supply voltages d1_gv dd d2_gv dd 2.5v 125 mv v (9) 1.8v 90 mv v (9) etsec 1 and 2 i/o supply voltage lv dd 3.3v 165 mv v (10) 2.5v 125 mv v (10) etsec 3 and 4 i/o supply voltage tv dd 3.3v 165 mv v (10) 2.5v 125 mv v (10) local bus, duart, dma, multiprocessor interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, jtag and miscellaneous i/o voltage ov dd 3.3v 165 mv v (5) input voltage ddr and ddr2 sdram signals d n _ mv in gnd to d n _gv dd v (3)(6) ddr and ddr2 sdram reference d n _ mv ref d n _gv dd /2 1% v three-speed ethernet signals lv in tv in gnd to lv dd gnd to tv dd v (4)(6) duart, local bus, dma, multiprocessor interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, jtag and miscellaneous i/o voltage ov in gnd to ov dd v (5)(6) operating temperature t j t c t c = -55 c to t j = 125 c c
8 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 2. if two separate power supplies are used for v dd _core0 and v dd _core1, they must be at the same nominal voltage and the individual power supplies must be tracked and kept within 100 mv of each other during normal run time. 3. caution: d n _ mv in must meet the overshoot/und ershoot requirements for d n _gv dd as shown in figure 3-1 . 4. caution: l/tv in must meet the overshoot/unde rshoot requirements for l/tv dd as shown in figure 3-1 during regular run time. 5. caution: ov in must meet the overshoot/undershoot requirements for ov dd as shown in figure 3-1 during regular run time. 6. timing limitations for m,l,t,o)v in and d n _mv ref during regular run time is provided in figure 3-1 . 7. applies to a core frequency of 1333 mhz and below. 8. applies to a core frequency above 1333 mhz. 9. the 2.5v 125 mv range is for ddr and 1.8v 90 mv range is for ddr2. 10. see section 9.2 ?fifo, gmii, mii, tbi, rgmii, rmii , and rtbi ac timing specifications? on page 27 for details on the rec- ommended operating conditions per protocol. 11. the pci express interface of the device is expected to rece ive signals from 0.175 to 1.2v. for more information refer to sec- tion 15.4.3 ?differential receiver (r x) input specifications? on page 59 . figure 3-1 shows the undershoot and overshoot voltages at the interfaces of the pc8641. figure 3-1. overshoot/undershoot voltage for dn_gv dd /ov dd /lv dd note: 1. t clk references clocks for various functional blocks as follows: ddr n = 10% of d n _mck period etsec n = 10% of ec n _gtx_clk125 period local bus = 10% of lclk[0:2] period serdes = 10% of sd n _ref_clk period i 2 c = 10% of sysclk jtag = 10% of sysclk gnd gnd ? 0.3v gnd ? 0.7v l/t/d n _g/o/x/sv dd + 20% l/t/d n _g/o/x/sv dd + 5% v ih v il not to exceed 10% of t clk (1) l/t/d n _g/o/s/xv dd
9 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] the pc8641 core voltage must always be provided at nominal v dd _core n (see table 3-2 on page 7 for actual recommended core voltage). voltage to the processor interface i/os are provided through sepa- rate sets of supply pins and must be provided at the voltages shown in table 3-2 . the input voltage threshold scales with respect to t he associated i/o supply voltage. ov dd and l/tv dd based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specifications. the ddr sdram inter- face uses a single-ended differential receiv er referenced to each externally supplied d n _mv ref signal (nominally set to d n _gv dd /2) as is appropriate for the (sstl-18 and sstl-25) electrical signaling standards. 3.1.3 output driver characteristics table 3-3 provides information on the characteristics of the output driver strengths. the values are pre- liminary estimates . notes: 1. see the ddr control driver registers in the pc8641d reference manual for more information. 2. only the following local bus signals have programmable dr ive strengths: lale, lad[0:31] , ldp[0:3], la[27:31], lcke, lcs[1:2], lwe[0:3], lgpl1, lgpl2, lgpl3, lgpl4, lgpl5, lclk[0:2]. the other local bus signals have a fixed drive strength of 45 . see the por impedance control register in the pc 8641d reference manual for more information about local bus signals and their drive strength programmability. 3. see section 18. ?signal listings? on page 75 for details on resistor requirements for the calibration of sd n _imp_cal_tx and sd n _imp_cal_rx transmit and receive signals. 4. stub series terminated logic (sstl-25) type pins. 5. stub series terminated logic (sstl-18) type pins. 6. low voltage transistor-transistor logic (lvttl) type pins. 7. open drain type pins. 8. low voltage differential signaling (lvds) type pins. 9. the drive strength of the ddr interf ace in half strength mode is at t j = 105c and at dn_gv dd (min). table 3-3. output drive capability driver type programmable output impedance ( ) supply voltage notes ddr1 signal 18 36 (half strength mode) d n _gv dd = 2.5v (4)(9) ddr2 signal 18 36 (half strength mode) d n _gv dd = 1.8v (1)(5)(9) local bus signals 45 25 ov dd = 3.3v (2)(6) etsec/10/100 signals 45 t/lv dd = 3.3v (6) 30 t/lv dd = 2.5v (6) duart, dma, multiprocessor interrupts, system control & clocking, debug, test, jtag, power management, jtag and miscellaneous i/o voltage 45 ov dd = 3.3v (6) i 2 c150ov dd = 3.3v (7) srio, pci express 100 sv dd = 1.1/1.05v (3)(8)
10 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 3.2 power up/down sequence the pc8641 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. note: the recommended maximum ramp up time for power supplies is 20 milliseconds. the chronological order of power up is: 1. all power rails other than ddr i/o (d n _gv dd , and d n _mv ref ). note: there is no required order sequence between the individual rails for this item (# 1). however, v dd_plat , av dd_plat rails must reach 90% of their recommended value before the rail for dn_gv dd , and dn_mvref (in next step) reaches 10% of their recommended value. av dd type supplies must be delayed with respect to their source supplies by the rc time constant of the pll filter circuit described in section 21.2.1 ?pll power supply filtering? on page 96 . 2. d n _gv dd , d n _mv ref note: it is possible to leave the related power supply (dn_gv dd , dn_mvref) turned off at reset for a ddr port that will not be used. note t hat these power supplies can only be powered up again at reset for functionality to occur on the ddr port. 3. sysclk the recommended order of power down is as follows: 1. dn_gv dd , dn_mv ref 2. all power rails other than ddr i/o (dn_gv dd , dn_mv ref ). note: sysclk may be powered down simultaneous to either of item # 1 or # 2 in the power down sequence. beyond this, the power supplies may power down simultaneously if the preservation of ddrn memory is not a concern. see figure 3-2 on page 11 for more details on the power and reset sequencing details.
11 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 3-2 illustrates the power up se quence as described above. figure 3-2. pc8641 power-up and reset sequence notes: 1. dotted waveforms correspond to optional supply values for a specified power supply. see table 3-2 on page 7 . 2. the recommended maximum ramp up time for power supplies is 20 milliseconds. 3. refer to section 6. ?reset initialization? on page 17 for additional information on pll relock and reset signal assertion timing requirements. 4. refer to table 6-1 on page 17 for additional information on reset configuration pin setup timing require- ments. in addition see figure 21-6 on page 104 regarding hreset and jtag connection details including trst . 5. e600 pll relock time is 100 microseconds maximum plus 255 mpx_clk cycles. 6. por configuration signals must be driven on reset. see section 6. ?reset initialization? on page 17 for more information on setup and hold time of reset configuration signals. 7. v dd _plat, av dd _plat must strictly reach 90% of their recommended voltage before the rail for d n _gv dd , and d n _mv ref reaches 10% of their recommended voltage. 8. sysclk must be driven only after the power for the various power supplies is stable. 9. in device sleep mode, the reset configuration signals for dram types (tsec2_txd[4],tsec2_tx_er) must be valid before hreset is asserted. dc power supply voltage v dd _plat, av dd _plat l/t/ov dd time 2.5 v 3.3 v 1.2 v 0 reset configuration pins h reset (& trst) 100 s platform pll asserted for power supply ramp up 2 e600 5 av dd _lb, sv dd , xv dd _srds n v dd _core n , av dd _core n av dd _srds n 1.8 v d n _gv dd , = 1.8/2.5 v d n _mv ref if sysclk 8 (not drawn to scale) relock time 3 l/tv dd =2.5 v 1 7 pll 9 sysclk is functional 4 cycles setup and hold time 6 100 s after
12 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 4. power characteristics the power dissipation for the dual co re pc8641d device is shown in table 4-1 . notes: 1. these values specify the power cons umption at nominal voltage and apply to all valid processor bus frequencies and conf ig- urations. the values do not include power dissipation for i/o supplies. 2. typical power is an average value measured at the nominal recommended core voltage (v dd _core n ) and 65 c junction temperature (see table 3-2 on page 7 ) while running the dhrystone 2.1 benchmar k and achieving 2.3 dhrystone mips/mhz with one core at 100% efficiency and the second core at 65% efficiency. 3. thermal power is the average power measured at nominal core voltage (v dd _core n ) and maximum operating junction tem- perature (see table 3-2 ) while running the dhrystone 2.1 benchmark and ac hieving 2.3 dhrystone mips/mhz on both cores and a typical workload on platform interfaces. 4. maximum power is the maximum power measured at nominal core voltage (v dd _core n ) and maximum operating junction temperature (see table 3-2 ) while running a test which includes an entirely l1-cache-resident, contrived sequence of instructions which keep all the execut ion units maximally busy on both cores. 5. these power numbers are for part number pc8641dxx1000nx only. v dd _core n = 0.95v and v dd _plat = 1.05v. table 4-1. pc8641d power dissipation (dual core) power mode core frequency (mhz) platform frequency (mhz) v dd _core n , v dd _plat (volts) junction temperature power (watts) notes typical 1500 mhz 600 mhz 1.1v 65 c32.1 (1)(2) thermal 105 c43.4 (1)(3)(5) maximum 110 c49.9 (1)(4)(5) 125 ctbc (1)(4)(5) typical 1333 mhz 533 mhz 1.05v 65 c23.9 (1)(2) thermal 105 c30 (1)(3)(5) maximum 110 c34.1 (1)(4)(5) 125 ctbc (1)(4) typical 1250 mhz 500 mhz 1.05v 65 c23.9 (1)(2) thermal 105 c30 (1)(3) maximum 110 c34.1 (1)(4) 125 ctbc (1)(4) typical 1000 mhz 400 mhz 1.05v 65 c23.9 (1)(2) thermal 105 c30 (1)(3) maximum 110 c34.1 (1)(4) 125 ctbc (1)(4) typical 1000 mhz 500 mhz 0.95v 1.05v 65 c16.2 (1)(2)(5) thermal 105 c21.8 (1)(3)(5) maximum 110 c25 (1)(4)(5) 125 ctbc (1)(4)(5)
13 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] the power dissipation for the pc8641 single core is shown in table 4-2 . notes: 1. this is a maximum power supply number which is provid ed for power supply and board design information. the numbers are based on 100% bus utilization for each component. the componen ts listed are not expected to have 100% bus usage simul- taneously for all components. actual numbers may vary based on activity. 2. number is based on a per port/interface value. 3. this is based on one etsec port used. since 16-bit fifo mode involves two ports, the number will need to be multiplied by two for the total. the other etsec protocol s dissipate less than this number per port. note that the power needs to be multi- plied by the number of ports used for the protoc ol for the total etsec port power dissipation. 4. this includes local bus, duart, jtag, i 2 c, dma, multiprocessor interrupts, syst em control & clocking, debug, test, power management, jtag and miscellaneous i/o voltage. 5. these power numbers are for part number pc8641xxx1000nx only. v dd _core n = 0.95v and v dd _plat = 1.05v. table 4-2. pc8641d individual supply maximum power dissipation (1) component description supply voltage (volts) power (watts) notes per core voltage supply v dd _core0/v dd _core1 = 1.1v at 1500 mhz 21.00 per core pll voltage supply av dd _core0/av dd _core1 = 1.1v at 1500 mhz 0.13 per core voltage supply v dd _core0/v dd _core1 = 1.05v at 1333 mhz 17.00 per core pll voltage supply av dd _core0/av dd _core1 = 1.05v at 1333 mhz 0.13 per core voltage supply v dd _core0/v dd _core1 = 0.95v at 1000 mhz 11.50 (5) per core pll voltage supply av dd _core0/av dd _core1 = 0.95v at 1000 mhz 0.13 (5) ddr controller i/o voltage supply d n _gv dd = 2.5v at 400 mhz 0.80 (2) d n _gv dd = 1.8v at 533 mhz 0.68 (2) d n _gv dd = 1.8v at 600 mhz 0.77 (2) 16-bit fifo at 200 mhz etsec 1&2/3&4 voltage supply l/tv dd = 3.3v 0.11 (2)(3) non-fifo etsec n voltage supply l/tv dd = 3.3v 0.08 (2) x8 serdes transceiver supply sv dd = 1.1v 0.70 (2) x8 serdes i/o supply xv dd _srds n = 1.1v 0.66 (2) serdes pll voltage supply port 1 or 2 av dd _srds1/av dd _srds2 = 1.1v 0.10 platform i/o supply ov dd = 3.3v 0.45 (4) platform source supply v dd _plat = 1.1v at 600 mhz 12.00 platform source supply v dd _plat = 1.05 vn at 500 mhz 9.80 (5) platform source supply v dd _plat = 1.05 vn at 400 mhz 7.70 platform, local bus pll voltage supply av dd _plat, av dd _lb = 1.1v 0.10
14 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 the estimated power dissipation for the pc 8641 single core device is shown in table 4-3 . the listed next to each number is to indicate that the number is based on an estimate. notes: 1. these values specify the power co nsumption at nominal voltage and apply to all valid processor bus frequencies andconfi g- urations. the values do not include power dissipation for i/o supplies. 2. typical power is an average value measured at the nominal recommended core voltage (v dd _core n ) and 65 c junctiontem- perature (see table 3-2 on page 7 )while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz. 3. thermal power is the average power measured at nominal core voltage (v dd _core n ) and maximum operating junctiontem- perature (see table 3-2 ) while running the dhrystone 2.1 benchmark and achieving 2.3 dhryst one mips/mhz and a typicalworkload on platform interfaces. 4. maximum power is the maximum power measured at nominal core voltage (v dd _core n ) and maximum operating junction- temperature (see table 3-2 ) while running a test which includes an entirely l1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy. 5. these power numbers are for part number pc8641xx1000nx only. v dd _core n = 0.95v and v dd _plat = 1.05v. table 4-3. pc8641 power dissipation (single core) power mode core frequency (mhz) platform frequency (mhz) v dd _core n , v dd _plat (volts) junction temperature power (watts) notes ty p i c a l 1333 mhz 533 mhz 1.05v 65 c16.3 (1)(2) thermal 105 c20.2 (1)(3) maximum 110 c23.2 (1)(4) 125 ctbc (1)(4) ty p i c a l 1250 mhz 500 mhz 1.05v 65 c16.3 (1)(2) thermal 105 c20.2 (1)(3) maximum 110 c23.2 (1)(4) 125 ctbc (1)(4) ty p i c a l 1000 mhz 400 mhz 1.05v 65 c16.3 (1)(2) thermal 105 c20.2 (1)(3) maximum 110 c23.2 (1)(4) 125 ctbc (1)(4) ty p i c a l 1000 mhz 500 mhz 0.95v 1.05v 65 c11.6 (1)(2)(5) thermal 105 c14.4 (1)(3)(5) maximum 110 c16.5 (1)(4)(5) 125 ctbc (1)(4)(5)
15 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 5. input clocks table 5-1 provides the system clock (sysclk) dc specifications for the pc8641. note: 1. note that the symbol ov in , in this case, represents the ov in symbol referenced in table 3-1 on page 6 and table 3-2 on page 7 . 5.1 system clock timing table 5-2 provides the system clock (sysclk) ac timing specificati ons for the pc8641. notes: 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chos en such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock freq uency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2 ?mpx to sysclk pll ratio? on page 87 and section 19.3 ?e600 to mpx clock pll ratio? on page 88 , for ratio settings. 2. rise and fall times for sysclk are measured at 0.4v and 2.7v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter: short term and long term, and is guaranteed by design. 5. the sysclk driver?s closed loop jitter bandwidth should be < 500 khz at -20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track sysclk drivers wi th the specified jitter. note that the frequency modulation for sysclk reduces significantly for the spread spectrum source case. this is to guarantee what is supported based on design. 5.1.1 sysclk and spread spectrum sources spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (emi) by spreading the emitted noise to a wider spectrum and reducing the peak noise magni- tude in order to meet industry and government requirements. these clock sources intentionally add long- term jitter in order to diffuse the emi spectral content. the jitter specification given in table 5-3 considers short-term (cycle-to-cycle) jitter only and the clock gene rator?s cycle-to-cycle outp ut jitter should meet the pc8641 input cycle-to-cycle jitter requirement. freq uency modulation and sp read are separate con- table 5-1. sysclk dc electrical characteristics (ov dd = 3.3v 165 mv) parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il -0.3 0.8 v input current (v in (1) = 0v or v in = v dd ) i in ?5a table 5-2. sysclk ac timing specifications (at recommended operating conditions with ov dd = 3.3v 165 mv. see table 3-2 on page 7 ) parameter/condition symbol min typical max unit notes sysclk frequency f sysclk 66 ? 166.66 mhz (1) sysclk cycle time t sysclk 6??ns? sysclk rise and fall time t kh , t kl 0.6 1.0 1.2 ns (2) sysclk duty cycle t khk /t sysclk 40 60 % (3) sysclk jitter ? ? ? 150 ps (4)(5)
16 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 cerns, and the pc8641 is compatible with spread spectrum sources if the recommendations listed in table 5-3 are observed. notes: 1. guaranteed by design. 2. sysclk frequencies resulting from frequency spreading, and the resulting core and vco frequencies, must meet the minimum and maxi mum specifications given in table 5-3 . it is imperative to note that the processor?s minimum and maximum sysclk, core, and vco frequen- cies must not be exceeded regardless of the type of clock source. therefore, systems in which the processor is operated at its maximum rated e600 core frequency should avoid violating the stated limits by using down-spreading only. sd n _ref_clk and sd n _ref_clk was designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30-33khz rate is allowed), assuming both ends have same reference clock. for better results use a source without significant unintended modulation. 5.2 real time clock timing the rtc input is sampled by the platform clock (mpx clock). the output of the sampling latch is then used as an input to the counters of the pic. there is no jitter specification. the minimum pulse width of the rtc signal should be greater than 2x the period of the mpx clock. that is, minimum clock high time is 2 t mpx , and minimum clock low time is 2 t mpx . there is no minimum rtc frequency; rtc may be grounded if not needed. 5.3 etsec gigabit refe rence clock timing table 5-4 provides the etsec gigabit reference cloc ks (ec_1_gtx_clk125 and ec_2_gtx_clk125) ac timing specifications for the pc8641. notes: 1. timing is guaranteed by design and characterization. 2. ec_gtx_clk125 is used to generate the gtx clock for t he etsec transmitter with 2% degradation. ec_gtx_clk125 duty cycle can be loosened from 47/53% as long as the ph y device can tolerate the dut y cycle generated by the etsec gtx_clk. see section 9.2.6 ?rgmii and rtbi ac timing specifications? on page 36 for duty cycle for 10base-t and 100base-t reference clock. table 5-3. spread spectrum clock source recommendations (at recommended operating conditions. see table 3-2 on page 7 ) parameter min max unit notes frequency modulation ? 50 khz (1) frequency spread ? 1.0 % (1)(2) table 5-4. ec_gtx_clk125 ac timing specifications parameter/condition symbol min typical max unit notes ecn_gtx_clk125 frequency f g125 ?125?mhz ecn_gtx_clk125 cycle time t g125 ?8?ns ec_gtx_clk125 duty cycle - gmii, tbi - 1000base-t for rgmii, rtbi t g125h /t g125 45 47 ?55 53 % (1)(2)
17 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] note: the phase between the output clocks tsec1_gtx_cl k and tsec2_gtx_clk (ports 1 and 2) is no more than 100 ps. the phase between the output clocks tsec3_gtx_clk and tsec4_gtx_clk (ports 3 and 4) is no more than 100 ps. 5.4 platform frequency requirements fo r pci-express and serial rapidio the mpx platform clock frequency must be considered for proper operation of the high-speed pci express and serial rapidio interfaces as described below. for proper pci express operation, the mpx clock frequency must be greater than or equal to: note that at mpx = 400 mhz, cfg_plat_freq = 0 and at mpx > 400 mhz, cfg_plat_freq = 1. therefore, when operating pci express in x8 link width, the mpx platform frequency must be 400 mhz with cfg_plat_freq = 0 or greater than or equal to 527 mhz with cfg_plat_freq = 1. for proper serial rapidio operation, the mpx clock frequency must be greater than: 5.5 other input clocks for information on the input clocks of other functi onal blocks of the platform such as serdes, and etsec, see the specific section of this document. 6. reset initialization this section describes the ac electrical specificatio ns for the reset initialization timing requirements of the pc8641. table 6-1 provides the reset initialization ac timing specifications for the ddr sdram component(s). notes: 1. sysclk is the primary clock input for the pc8641. 2. this is related to hreset assertion time. stable pll configuration inpu ts are required when a stable sysclk is applied. see the pc8641d integrated host processor reference manual for more details on the power-on reset sequence. 527 mhz (pci-express link width) 16 / (1 + cfg_plat_freq) ---------------------------------------------------------------------------------------------- - 2 (0.80) (serial rapidio interface frequency) (serial rapidio link width) 64 ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------ - table 6-1. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset 100 ? s minimum assertion time for sreset_0 & sreset_1 3 ? sysclks (1) platform pll input se tup time with stable sysclk before hreset negation 100 ? s (2) input setup time for por config s (other than pll config) with respect to negation of hreset 4 ? sysclks (1) input hold time for all por conf igs (including pll config) with respect to negation of hreset 2 ? sysclks (1) maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks (1)
18 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 table 6-2 provides the pll lock times. note: 1. the pll lock time for e600 plls require an additional 255 mpx_clk cycles. 7. ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the dd r sdram interface of the pc8641. note that ddr sdram is dn_gv dd (typ) = 2.5v and ddr2 sdram is dn_gv dd (typ) = 1.8v. 7.1 ddr sdram dc elect rical characteristics table 7-1 provides the recommended op erating conditions for the ddr sdram component(s) of the pc8641 when dn_gv dd (typ) = 1.8v. notes: 1. d n _gv dd is expected to be within 50 mv of the dram d n _gv dd at all times. 2. d n _mv ref is expected to be equal to 0.5 d n _gv dd , and to track d n _gv dd dc variations as measured at the receiver. peak-to-peak noise on d n _mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to d n _mv ref . this rail should track variations in the dc level of d n _mv ref .. table 6-2. pll lock times parameter/condition min max unit notes (platform and e600) pll lock times ? 100 s (1) local bus pll ? 50 s table 7-1. ddr2 sdram dc electrical characteristics for d n _gv dd (typ) = 1.8v parameter/condition symbol min max unit notes i/o supply voltage d n _gv dd 1.71 1.89 v (1) i/o reference voltage d n _mv ref 0.49 d n _gv dd 0.51 d n _gv dd v (2) i/o termination voltage v tt d n _mv ref ? 0.04 d n _mv ref + 0.04 v (3) input high voltage v ih d n _mv ref + 0.125 d n _gv dd + 0.3 v input low voltage v il -0.3 d n _mv ref - 0.125 v output leakage current i oz -9.9 9.9 a (4) output high current (v out = 1.420v) i oh -13.4 ? ma output low current (v out = 0.280v) i ol 13.4 ? ma
19 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 4. output leakage is measured with all outputs disabled, 0v v out d n _gv dd . table 7-2 provides the ddr capacitance when gv dd (typ) = 1.8v. note: 1. this parameter is sampled.d n _ gv dd = 1.8v 0.090v, f = 1 mhz, t a = 25 c, v out = d n _gv dd /2, v out (peak-to-peak) = 0.2v. table 7-3 provides the recommended operating condit ions for the ddr sdram component(s) when d n _gv dd (typ) = 2.5v. notes: 1. d n _gv dd is expected to be within 50 mv of the dram d n _gv dd at all times. 2. mv ref is expected to be equal to 0.5 d n _gv dd , and to track d n _gv dd dc variations as measured at the receiver. peak-to- peak noise on d n _mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to d n _mv ref . this rail should track variations in the dc level of d n _mv ref . 4. output leakage is measured with all outputs disabled, 0v v out gv dd . table 7-4 provides the ddr capacitance when d n _g v dd (typ) = 2.5v. note: 1. this parameter is sampled. d n _gv dd = 2.5v 0.125v, f = 1 mhz, t a = 25 c, v out = d n _gv dd /2, v out (peak-to-peak) =0.2v. table 7-2. ddr2 sdram capacitance for d n _gv dd (typ) = 1.8v parameter/condition symbol min max unit notes input/output capacita nce: dq, dqs, dqs c io 68pf (1) delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf (1) table 7-3. ddr sdram dc electrical characteristics for d n _gv dd (typ) = 2.5v parameter/condition symbol min max unit notes i/o supply voltage d n _gv dd 2.375 2.625 v (1) i/o reference voltage d n _mv ref 0.49 d n _gv dd 0.51 d n _gv dd v (2) i/o termination voltage v tt d n _mv ref ? 0.04 d n _mv ref + 0.04 v (3) input high voltage v ih d n _mv ref + 0.15 d n _gv dd + 0.3 v input low voltage v il -0.3 d n _mv ref ? 0.15 v output leakage current i oz -9.9 9.9 a (4) output high current (v out = 1.95v) i oh -16.2 ? ma output low current (v out = 0.35v) i ol 16.2 ? ma table 7-4. ddr sdram capacitance for d n _gv dd (typ) = 2.5v parameter/condition symbol min max unit notes input/output capaci tance: dq, dqs c io 68pf (1) delta input/output capacitance: dq, dqs c dio ?0.5pf (1)
20 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 table 7-5 provides the current draw characteristics for mv ref . note: 1. the voltage regulator for mv ref must be able to supply up to 500 a current. 7.2 ddr sdram ac elect rical characteristics this section provides the ac electrical characteristics for th e ddr sdram interface. 7.2.1 ddr sdram input ac timing specifications table 7-6 provides the input ac timing specifications for the ddr sdram when dn_gv dd (typ) =1.8v.. table 7-7 provides the input ac timing spec ifications for the ddr sdram when d n _gv dd (typ) = 2.5v. table 7-8 provides the input ac timing specif ications for the ddr sdram interface. table 7-5. current draw characteristics for mv ref parameter/condition symbol min max unit note current draw for mv ref i mvref ?500a (1) table 7-6. ddr2 sdram input ac timing specifications for 1.8v interface (at recommended operating conditions) parameter symbol min max unit ac input low voltage v il ? d n _mv ref ? 0.25 v ac input high voltage v ih d n _mv ref + 0.25 v table 7-7. ddr sdram input ac timing specifications for 2.5v interface (at recommended oper- ating conditions) parameter symbol min max unit ac input low voltage v il ? d n _mv ref ? 0.31 v ac input high voltage v ih d n _mv ref + 0.31 v table 7-8. ddr sdram input ac timing specifications (at recommended operating conditions) parameter symbol min max unit notes controller skew for mdqs-mdq/mecc t ciskew ps (1)(2)
21 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any cor- responding bit that will be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew .this can be determined by the following equation: t diskew = (t/4 - abs( t ciskew ) where t is the clock period and abs( t ciskew ) is the absolute value of t ciskew . 3. maximum ddr1 frequency is 400 mhz. 600 mhz - 240 240 (3) 533 mhz - 300 300 (3) 400 mhz - 365 365 table 7-8. ddr sdram input ac timing specifications (at recommended operating conditions) parameter symbol min max unit notes
22 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 7.2.2 ddr sdram output ac timing specifications notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) un til the output went invalid ( ax or dx). for example, t ddkhas symbol- izes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. table 7-9. ddr sdram output ac timing specificatio ns (at recommended operating conditions) parameter symbol (1) min max unit notes mck[n] cycle time, mck[n]/mck [n] crossing t mck 310ns (2) mck duty cycle 600 mhz 533 mhz 400 mhz t mckh /t mck 47.5 47 47 52.5 53 53 % (8) (9) (9) addr/cmd output setup with respect to mck 600 mhz 533 mhz 400 mhz t ddkhas 1.10 1.48 1.95 ? ? ? ns (3) (7) (7) addr/cmd output hold with respect to mck 600 mhz 533 mhz 400 mhz t ddkhax 1.10 1.48 1.95 ? ? ? ns (3) (7) (7) mcs [n] output setup with respect to mck 600 mhz 533 mhz 400 mhz t ddkhcs 1.10 1.48 1.95 ? ? ? ns (3) (7) (7) mcs [n] output hold with respect to mck 600 mhz 533 mhz 400 mhz t ddkhcx 1.10 1.48 1.95 ? ? ? ns (3) (7) (7) mck to mdqs skew t ddkhmh - 0.6 0.6 ns (4) mdq/mecc/mdm output set up with respect to mdqs 600 mhz 533 mhz 400 mhz t ddkhds , t ddklds 500 590 700 ? ? ? ps (5) (7) (7) mdq/mecc/mdm output hold with respect to mdqs 600 mhz 533 mhz 400 mhz t ddkhdx , t ddkldx 500 590 700 ? ? ? ps (5) (7) (7) mdqs preamble start t ddkhmp -0.5 t mck ? 0.6 -0.5 x t mck +0.6 ns (6) mdqs epilogue end t ddkhme -0.6 0.6 ns (6)
23 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[n] clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqs override bits (called wr_data_delay) in the timi ng_cfg_2 register. this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these 2 parame- ters have been set to the same adjustment value. see the pc8641 integrated processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data st robe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck[ n] at the pins of the microprocessor. note that t ddkhmp follows the sym- bol conventions described in note 1. 7. maximum ddr1 frequency is 400 mhz. 8. per the jedec spec the ddr2 duty cycle at 600 mhz is the av erage low and high cycle time values that are defined as the average pulse widths calculated across any consecutive 200 pulses. jitter can sometimes force single low and high cycle times to drift from the average values. t jit = 125 ps. 9. per the jedec spec the ddr2 duty cycle at 400 and 533 mhz is the low and high cycle time values. note: for the addr/cmd setup and hold specifications in table 7-9 on page 22 , it is assumed that the clock con- trol register is set to adjust t he memory clocks by 1/2 applied cycle. figure 7-1 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 7-1. timing diagram for t ddkhmh mdqs mck[n] mck[n] t mck mdqs t ddkhmh(max) = 0.6 ns t ddkhmh(min) = -0.6 ns
24 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 7-2 shows the ddr sdram output timing diagram. figure 7-2. ddr sdram output timing diagram figure 7-3 provides the ac test load for the ddr bus. figure 7-3. ddr ac test load addr/cmd t ddkhas , t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck[n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax , t ddkhcx write a0 noop t ddkhmp t ddkhme output z 0 = 50 dn_gv dd /2 r l = 50
25 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 8. duart this section describes the dc and ac electrical s pecifications for the duart interface of the pc8641. 8.1 duart dc electri cal characteristics table 8-1 provides the dc electrical characteristics for the duart interface. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 6 and table 3-2 on page 7 . 8.2 duart ac electrical specifications table 8-2 provides the ac timing parameters for the duart interface. notes: 1. guaranteed by design. 2. mpx clock refers to the platform clock. 3. actual attainable baud rate will be limited by the latency of interrupt processing. 4. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 trans ition of the start bit. sub- sequent bit values are sampled each 16 th sample. table 8-1. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2 ov dd + 0.3 v low-level input voltage v il - 0.3 0.8 v input current ( v in (1) = 0v or v in = v dd ) i in ? 5 a high-level output voltage (ov dd = mn, i oh = -100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ? 0.2 v table 8-2. duart ac timing specifications parameter value unit notes minimum baud rate mpx clock/1,048,576 baud (1)(2) maximum baud rate mpx clock/16 baud (1)(3) oversample rate 16 ? (1)(4)
26 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 9. ethernet: enhanced th ree-speed ethernet (e tsec), mii management this section provides the ac and dc electrical characteristic s for enhanced three-speed and mii management. 9.1 enhanced three-speed ethernet controller (etsec) (10/100/1gb mbps) ? gmii/mii/tbi/ rgmi i/rtbi/rmii electri cal characteristics the electrical characteristics s pecified here apply to all gigabi t media independent interface (gmii), media independent interface (mii), ten-bit interface (tbi), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), and reduced media independent interface (rmii) signals except management data input/output (mdio) and management data clock (mdc). the rgmii and rtbi interfaces are defined for 2.5v, while the gmii, mii, rmii and tbi interfaces can be operated at 3.3 or 2.5v. whether the gmii, mii, or tbi interface is operated at 3.3 or 2.5v, the timing is compliant with the ieee 802.3 standard. the rgmii and rtbi interfaces follow the reduced gigabit media-indepen- dent interface (rgmii) specification version 1.3 (12/10/2000). the rmii interface follows the rmii consortium rmii specification version 1.2 (3/20/1998 ). the electrical characte ristics for mdio and mdc are specified in section 10. ?ethernet management interface electrical characteristics? on page 39 . 9.1.1 etsec dc electrical characteristics all gmii, mii, tbi, rgmii, rmii and rtbi drivers an d receivers comply with the dc parametric attributes specified in table 9-1 and table 9-2 on page 27 . the potential applied to the input of a gmii, mii, tbi, rgmii, rmii or rtbi receiver may exceed the potential of the receiver?s power supply (i.e., a gmii driver powered from a 3.6-v supply driving v oh into a gmii receiver powered from a 2.5v supply). tolerance for dissimilar gmii driver and receiver supply potentia ls is implicit in these specifications. the rgmii and rtbi signals are based on a 2.5v cmos interf ace voltage as defined by jedec eia/jesd8-5. notes: 1. lv dd supports etsecs 1 and 2. 2. tv dd supports etsecs 3 and 4. 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in table 3-1 on page 6 and table 3-2 on page 7 . table 9-1. gmii, mii, rmii, and tbi dc electrical characteristics parameter symbol min max unit notes supply voltage 3.3v lv dd tv dd 3.135 3.465 v (1)(2) output high voltage (lv dd /tv dd = min, i oh = -4.0 ma) v oh 2.40 lv dd /tv dd + 0.3 v output low voltage (lv dd /tv dd = min, i ol = 4.0 ma) v ol gnd 0.50 v input high voltage v ih 1.70 lv dd /tv dd + 0.3 v input low voltage v il -0.3 0.90 v input high current (v in = lv dd , v in = tv dd ) i ih ?40a (1)(2)(3) input low current (v in = gnd) i il -600 ? a (3)
27 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] . notes: 1. lv dd supports etsecs 1 and 2. 2. tv dd supports etsecs 3 and 4. 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in table 3-1 on page 6 and table 3-2 on page 7 . 9.2 fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications the ac timing specifications for fifo, gmii, mi i, tbi, rgmii, rmii and rtbi are presented in this section. 9.2.1 fifo ac specifications the basis for the ac specifications for the etsec?s fifo modes is the double data rate rgmii and rtbi specifications, since they have similar performanc e and are described in a source-synchronous fashion like fifo modes. however, the fifo interface provides deliberate skew between the transmitted data and source clock in gmii fashion. when the etsec is configured for fifo modes, all clocks are supplied from external sources to the rel- evant etsec interface. that is, the transmit cl ock must be applied to the etsecn?s tsecn_tx_clk, while the receive clock must be applied to pin tsecn_rx_clk. the etsec internally uses the transmit clock to synchronously generate transmit data and out puts an echoed copy of the transmit clock back out onto the tsecn_gtx_clk pin (while transmit data appears on tsecn_txd[7:0], for example). it is intended that external receivers capture etsec tr ansmit data using the clock on tsecn_gtx_clk as a source- synchronous timing referenc e. typically, the clock edge that launched the data can be used, since the clock is delayed by the etsec to allow ac ceptable set-up margin at the receiver. note that there is relationship between the maximum fifo s peed and the platform speed. for more information see section 19.4.2 ?platform to fifo restrictions? on page 89 . note: the phase between the output clocks tsec1_gtx_cl k and tsec2_gtx_clk (ports 1 and 2) is no more than 100 ps. the phase between the output clocks tsec3_gtx_clk and tsec4_gtx_clk (ports 3 and 4) is no more than 100 ps. table 9-2. gmii, mii, rmii, rgmii, rtbi, tbi and fifo dc electrical characteristics parameter symbol min max unit notes supply voltage 2.5v lv dd tv dd 2.375 2.675 v (1)(2) output high voltage (lv dd /tv dd = min, i oh = -1.0 ma) v oh 2lv dd /tv dd + 0.3 v output low voltage (lv dd /tv dd = min, i ol = 1.0 ma) v ol gnd - 0.3 0.40 v input high voltage v ih 1.70 lv dd /tv dd + 0.3 v input low voltage v il -0.3 0.70 v input high current (v in = lv dd , v in = tv dd ) i ih ?10a (1)(2)(3) input low current (v in = gnd) i il -15 ? a (3)
28 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 a summary of the fifo ac specifications appears in table 9-3 and table 9-4 . timing diagrams for fifo appear in figure 9-1 and figure 9-2 on page 29 . figure 9-1. fifo transmit ac timing diagram table 9-3. fifo mode transmit ac timing specification parameter/condition symbol min typ max unit input low voltage at 2.5 ov dd v il ??0.7v input high voltage at 2.5 ov dd v ih 1.9 ? ? v tx_clk, gtx_clk clock period t fit 5.0 8.0 100 ns tx_clk, gtx_clk duty cycle t fith /t fit 45 50 55 % tx_clk, gtx_clk peak-to-peak jitter t fitj ? ? 250 ps rise time tx_clk (20%?80%) t fitr ? ? 0.75 ns fall time tx_clk (80%?20%) t fitf ? ? 0.75 ns fifo data txd[7:0], tx_er, tx_en setup time to gtx_clk t fitdv 2.0 ? ? ns gtx_clk to fifo data txd[7: 0], tx_er, tx_en hold time t fitdx 0.5 ? 3.0 ns table 9-4. fifo mode receive ac timing specification parameter/condition symbol min typ max unit input low voltage at 2.5 ov dd v il ?? 0.7 v input high voltage at 2.5 ov dd v ih 1.9 ?? v rx_clk clock period t fir 5.0 8.0 100 ns rx_clk duty cycle t firh /t fir 45 50 55 % rx_clk peak-to-peak jitter t firj ?? 250 ps rise time rx_clk (20%?80%) t firr ?? 0.75 ns fall time rx_clk (80%?20%) t firf ?? 0.75 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t firdv 1.5 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t firdx 0.5 ? ? ns txd[7:0] tx_en gtx_clk tx_er t fit t fitf t fitr t fith t fitdv t fitdx
29 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 9-2. fifo receive ac timing diagram 9.2.2 gmii ac timing specifications this section describes the gmii transmit and receive ac timing specifications. 9.2.2.1 gmii transmit ac timing specifications table 9-5 provides the gmii transmit ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock ref- erence (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that, i n general, the clock reference symbol representation is based on th ree letters representing the clock of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for ri se and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-3 shows the gmii transmit ac timing diagram. figure 9-3. gmii transmit ac timing diagram rxd[7:0] rx_dv rx_clk rx_er t fir t firf t firr t firdv t firdx valid data t firh table 9-5. gmii transmit ac timing specifications (at recommended operating conditions with l/tv dd of 3.3v 5% and 2.5v 5%) parameter/condition symbol (1) min typ max unit input low voltage v il ?? 0.7 v input high voltage v ih 1.9 ?? v gmii data txd[7:0], tx_er, tx_en setup time t gtkhdv 2.5 ?? ns gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 0.5 ? 5.0 ns gtx_clk data clock rise time (20%-80%) t gtxr (2) ?? 1.0 ns gtx_clk data clock fall time (80%-20%) t gtxf (2) ?? 1.0 ns txd[7:0] tx_en gtx_clk tx_er t gtx t gtxh t gtkhdv t gtkhdx t gtxf t gtxr
30 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 9.2.2.2 gmii receive ac timing specifications table 9-6 provides the gmii receive ac timing specifications. . notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letter s representing the clock of a particular functional. for exam- ple, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-4 provides the ac test load for etsec. figure 9-4. etsec ac test load figure 9-5 shows the gmii receive ac timing diagram. figure 9-5. gmii receive ac timing diagram table 9-6. gmii receive ac timing specifications (at recommended operating conditions with l/tv dd of 3.3v 5% and 2.5v 5%) parameter/condition symbol (1) min typ max unit input low voltage v il ?? 0.7 v input high voltage v ih 1.9 ?? v rx_clk clock period t grx ? 8.0 ? ns rx_clk duty cycle t grxh /t grx 40 ? 60 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ?? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.5 ?? ns rx_clk clock rise (20%-80%) t grxr (2) ?? 1.0 ns rx_clk clock fall time (80%-20%) t grxf (2) 1.0 ns lv dd /2 output z 0 = 50 r l = 50 rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkv rx_dv rx_er
31 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 9.2.3 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 9.2.3.1 mii receive ac timing specifications table 9-7 provides the mii transmit ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letter s representing the clock of a particular functional. for exam- ple, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-6 shows the mii transmit ac timing diagram. figure 9-6. mii transmit ac timing diagram table 9-7. mii transmit ac timing specifications (at recommended operating conditions with l/tv dd of 3.3v 5% and 2.5v 5%) parameter/condition symbol (1) min typ max unit input low voltage v il ??0.7v input high voltage v ih 1.9 ? ? v tx_clk clock period 10 mbps t mtx (2) ? 400 ? ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh /t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise (20%-80%) t mtxr (2) 1?4ns tx_clk data clock fall (80%-20%) t mtxf (2) 1?4ns tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
32 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 9.2.3.2 mii receive ac timing specifications table 9-8 provides the mii receive ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with re spect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-7 provides the ac test load for etsec. figure 9-7. etsec ac test load figure 9-8 shows the mii receive ac timing diagram. figure 9-8. mii receive ac timing diagram table 9-8. mii transmit ac timing specifications (at recommended operating conditions with l/tv dd of 3.3v 5% and 2.5v 5%) parameter/condition symbol (1) min typ max unit input low voltage v il ??0.7v input high voltage v ih 1.9 ? ? v rx_clk clock period 10 mbps t mrx (2) ? 400 ? ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10 ? ? ns rx_clk clock rise (20%-80%) t mrxr (2) 1?4ns rx_clk clock fall time (80%-20%) t mrxf (2) 1?4ns lv dd /2 output z 0 = 50 r l = 50 rx_clk rxd[3:0] t mrdxkl t mrx t mrxh t mrxr t mrxf t mrdvkh rx_dv rx_er valid data
33 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 9.2.4 tbi ac timi ng specifications this section describes the tbi transmit and receive ac timing specifications. 9.2.4.1 tbi transmit ac timing specifications table 9-9 provides the tbi transmit ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state )(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit tim- ing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold ti me. note that, in general, the clock reference symbol repre- sentation is based on three letters repr esenting the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (t x) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. figure 9-9 shows the tbi transmit ac timing diagram. figure 9-9. tbi transmit ac timing diagram table 9-9. tbi transmit ac timing specifications (a t recommended operating conditions with l/tv dd of 3.3v 5% and 2.5v 5%) parameter/condition symbol (1) min typ max unit tcg[9:0] setup time gtx_clk going high t ttkhdv 2.0 ?? ns tcg[9:0] hold time from gtx_clk going high t ttkhdx 1.0 ?? ns gtx_clk rise (20%?80%) t ttxr (2) ?? 1.0 ns gtx_clk fall time (80%?20%) t ttxf (2) ?? 1.0 ns gtx_clk t ttx t ttxh t ttxr t ttxf t ttkhdv tcg[9:0] t ttxf t ttkhdx t ttxr
34 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 9.2.4.2 tbi receive ac timing specifications table 9-10 provides the tbi receive ac timing specifications. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) st ate. note that, in general, the clock refer- ence symbol representation is based on thr ee letters representing the clock of a pa rticular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. guaranteed by design. figure 9-10 shows the tbi receive ac timing diagram. figure 9-10. tbi receive ac timing diagram table 9-10. tbi receive ac timing specif ications (at recommended operating conditions with l/tv dd of 3.3v 5% and 2.5v 5%) parameter/condition symbol (1) min typ max unit pma_rx_clk[0:1] clock period t trx ? 16.0 ? ns pma_rx_clk[0:1] skew t sktrx 7.5 ? 8.5 ns pma_rx_clk[0:1] duty cycle t trxh/ t trx 40 ? 60 % rcg[9:0] setup time to rising pma_rx_clk t trdvkh 2.5 ? ? ns rcg[9:0] hold time to rising pma_rx_clk t trdxkh 1.5 ? ? ns pma_rx_clk[0:1] clock rise time (20%-80%) t trxr (2) 0.7 ? 2.4 ns pma_rx_clk[0:1] clock fall time (80%-20%) t trxf (2) 0.7 ? 2.4 ns valid data valid data pma_rx_clk1 rcg[9:0] t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh t trx
35 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 9.2.5 tbi single-clock mode ac specifications when the etsec is configured for tbi modes, all clocks are supplied from external sources to the rele- vant etsec interface. in single-clock tbi mode, when tbicon[clksel] = 1 a 125-mhz tbi receive clock is supplied on tsecn_rx_clk pin (no receive clock is used on tsecn_tx_clk in this mode, whereas for the dual-clock mode this is the pma1 receive clock). the 125-mhz transmit clock is applied on the tsec_gtx_clk125 pin in all tbi modes. a summary of the single-clock tbi mode ac specifications for receive appears in table 9-11 . a timing diagram for tbi receive appears in figure 9-11 . figure 9-11. tbi single-clock mode rece ive ac timing diagram table 9-11. tbi single-clock mode receiv e ac timing specification parameter/condition symbol min typ max unit input low voltage at 3.3 ov dd v il ??0.7v input high voltage at 3.3 ov dd v ih 1.9 ? ? v rx_clk clock period t trr 7.5 8.0 8.5 ns rx_clk duty cycle t trrh /t trr 40 50 60 % rx_clk peak-to-peak jitter t trrj ??250ps rise time rx_clk (20%?80%) t trrr ??1.0ns fall time rx_clk (80%?20%) t trrf ??1.0ns rcg[9:0] setup time to rx_clk rising edge t trrdvkh 2.0 ? ? ns rcg[9:0] hold time to rx_clk rising edge t trrdxkh 1.0 ? ? ns t trr t trrh t trrf t trrr rx_clk rcg[9:0] t trrdxkh t trrdvkh valid data
36 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 9.2.6 rgmii and rtbi ac timing specifications table 9-12 presents the rgmii and rtbi ac timing specifications notes: 1. note that, in general, the clock reference symbol repres entation for this section is based on the symbols rgt to repres ent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the nota- tion for rise (r) and fall (f) times follows the clock symbol th at is being represented. for sym bols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be ro uted such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transi- tioned between. 5. guaranteed by characterization. figure 9-12 shows the rgmii and rtbi ac ti ming and multiplexing diagrams. figure 9-12. rgmii and rtbi ac timing and multiplexing diagrams table 9-12. rgmii and rtbi ac timing specifications (a t recommended operating conditions with l/tv dd of 2.5v 5%) parameter/condition symbol (1) min typ max unit data to clock output skew (at transmitter) t skrgt (5) -500 0 500 ps data to clock input skew (at receiver) (2) t skrgt 1?2.8ns clock period (3) t rgt (5) 7.288.8ns duty cycle for 10base-t and 100base-tx (3)(4) t rgth /t rgt (5) 40 50 60 % rise time (20%-80%) t rgtr (5) ? ? 0.75 ns fall time (20%-80%) t rgtf (5) ? ? 0.75 ns gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt
37 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 9.2.7 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. 9.2.7.1 rmii transmit ac timing specifications the rmii transmit ac timing specifications are in table 9-13 . note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(sig- nal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii in general, the clock refer ence symbol representation is based on two to three letters representing the clock of a partic ular functional. for example, the subscript of t mtx repre- sents the mii(m) transmit (tx) clock. for rise and fall times, the latter conv ention is used with the appropriate letter: r (rise) or f (fall). figure 9-13 shows the rmii transmit ac timing diagram. figure 9-13. rmii transmit ac timing diagram table 9-13. rmii transmit ac timing specifications (at recommended operating conditions with l/tv dd of 3.3v 5% and 2.5v 5%) parameter/condition symbol (1) min typ max unit input low voltage at 3.3 ov dd v il ??0.8v input high voltage at 3.3 ov dd v ih 2.0 ? ? v ref_clk clock period t rmt 20.0 ns ref_clk duty cycle t rmth /t rmt 35 50 65 % ref_clk peak-to-peak jitter t rmtj ??250ps rise time ref_clk (20%?80%) t rmtr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmtf 1.0 ? 2.0 ns ref_clk to rmii data txd[1:0], tx_en delay t rmtdx 1 ? 10 ns ref_clk txd[1:0] t rmtdx t rmt t rmth t rmtr t rmtf tx_en tx_er
38 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 9.2.7.2 rmii receive ac timing specifications note: 1. the symbols used for timing specif icationsherein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with re spect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letter s representing the clock of a particular functional. for exam- ple, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). figure 9-14 provides the ac test load for etsec. figure 9-14. etsec ac test load figure 9-15 shows the rmii receive ac timing diagram. figure 9-15. rmii receive ac timing diagram table 9-14. rmii receive ac timing specifications (a t recommended operating conditions with l/tv dd of 3.3v 5% and 2.5v 5%) parameter/condition symbol (1) min typ max unit input low voltage at 3.3 ov dd v il ??0.8v input high voltage at 3.3 ov dd v ih 2.0 ? ? v ref_clk clock period t rmr 15.0 20.0 25.0 ns ref_clk duty cycle t rmrh /t rmr 35 50 65 % ref_clk peak-to-peak jitter t rmrj ??250ps rise time ref_clk (20%?80%) t rmrr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmrf 1.0 ? 2.0 ns rxd[1:0], crs_dv, rx_er setup ti me to ref_clk rising edge t rmrdv 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk rising edge t rmrdx 2.0 ? ? ns lv dd /2 output z 0 = 50 r l = 50 r ef_clk rxd[1:0] t rmrdx t rmr t rmrh t rmrr t rmrf crs_dv rx_er t rmrdv valid data
39 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 10. ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (manage- ment data input/output) and mdc (management data clock) . the electrical char acteristics for gmii, rgmii, rmii, tbi and rtbi are specified in section 9. ?ethernet: enhanced three-speed ethernet (etsec), mii management? on page 26 . 10.1 mii management dc el ectrical characteristics the mdc and mdio are defined to operate at a supply vo ltage of 3.3v. the dc electrical characteristics for mdio and mdc are provided in table 10-1 . note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 6 and table 3-2 on page 7 . 10.2 mii management ac electrical specifications table 10-2 provides the mii management ac timing specifications. table 10-1. mii management dc electrical characteristics parameter symbol min max unit supply voltage (3.3v) ov dd 3.135 3.465 v output high voltage (ov dd = min, i oh = -1 ma) v oh 2.10 ov dd + 0.3 v output low voltage (ov dd = min, i ol = 1 ma) v ol gnd 0.50 v input high voltage v ih 1.70 ? v input low voltage v il ?0.90v input high current (ov dd = max, v in (1) = 2.1v) i ih ?40a input low current (ov dd = max, v in = 0.5v) i il -600 ? a table 10-2. mii management ac timing specifications (at recommended operating conditions with ov dd is 3.3v 5%) parameter/condition symbol (1) min typ max unit notes mdc frequency f mdc 2.5 ? 9.3 mhz (2)(4) mdc period t mdc 80 ? 400 ns mdc clock pulse width high t mdch 32 ? ? ns mdc to mdio valid t mdkhdv 2*(t mpxclk *8) ? ns (5) mdc to mdio delay t mdkhdx 10 ? 2*(t mpxclk *8) ns (3)(5) mdio to mdc setup time t mddvkh 5? ?ns mdio to mdc hold time t mddxkh 0? ?ns mdc rise time t mdcr ?? 10ns (4) mdc fall time t mdhf ?? 10ns (4)
40 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setu p time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the system clock speed. (the maximum frequency is the maximum platform frequency divided by 64.) 3. this parameter is dependent on the system clock speed. (that is, for a system clock of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; for a system clock of 375 mhz, the maximum frequency is 11.7 mhz and the minimum frequency is 1.7 mhz). 4. guaranteed by design. 5. t mpxclk is the platform (mpx) clock. figure 10-1 provides the ac test load for etsec. figure 10-1. etsec ac test load note: output will see a 50 load since what it sees is the transmission line. figure 10-2 shows the mii management ac timing diagram. figure 10-2. mii management interface timing diagram ov dd /2 output z 0 = 50 r l = 50 mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output) t mdkhdv
41 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 11. local bus this section describes the dc and ac electrical spec ifications for the local bus interface of the pc8641. 11.1 local bus dc electrical characteristics table 11-1 provides the dc electrical characteristics for the local bus interface operating at ov dd = 3.3v dc note: 1. note that the symbol ov in , in this case, represents the ov in symbol referenced in table 3-1 on page 6 and table 3-2 on page 7 . 11.2 local bus ac elect rical specifications table 11-2 describes the general timing parameters of the local bus interface at ov dd = 3.3v dc. for information about the frequency range of local bus see section 19.1 ?clock ranges? on page 86 . table 11-1. local bus dc electrical characteristics (3.3v dc) parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il -0.3 0.8 v input current (ov in (1) = 0v or bv in = bv dd ) i in ? 5a high-level output voltage (ov dd = min, i oh = -2 ma) v oh ov dd - 0.2 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.2v table 11-2. local bus general timing parameters (ov dd = 3.3v dc) parameter configuration symbol (1) min max unit notes local bus cycle time t lbk 7.5 ? ns (2) local bus duty cycle t lbkh /t lbk 45 55 % lclk[n] skew to lclk[m] or lsync_out t lbkskew ?150ps (7)(8) input setup to local bus clock (except lupwait) t lbivkh1 1.8 ? ns (3)(4) lupwait input setup to local bus clock t lbivkh2 1.7 ? ns (3)(4) input hold from local bus clock (except lupwait) t lbixkh1 1.0 ? ns (3)(4) lupwait input hold from local bus clock t lbixkh2 1.0 ? ns (3)(4) lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns (6) local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?2.0ns local bus clock to data valid for lad/ldp t lbkhov2 ?2.2ns local bus clock to address valid for lad t lbkhov3 ?2.3ns local bus clock to lale assertion t lbkhov4 ?2.3ns (3)
42 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the out- put (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from ov dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between t he negation of lale and any change in lad. t lbotot is pro- grammed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between comple- mentary signals at bv dd /2. 8. guaranteed by design. figure 11-1 provides the ac test load for the local bus. figure 11-1. local bus ac test load note: pll bypass mode is recommended when lbiu frequency is at or below 83 mhz. when lbiu operates above 83 mhz, lbiu pll is recommended to be enabled. output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.7 ? ns output hold from local bus clock for lad/ldp t lbkhox2 0.7 ? ns local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.5ns (5) local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.5ns (5) table 11-2. local bus general timing parameters (ov dd = 3.3v dc) (continued) parameter configuration symbol (1) min max unit notes bv dd /2 output z 0 = 50 r l = 50
43 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 11-2 to figure 11-4 on page 46 show the local bus signals. figure 11-2. local bus signals, non-special signals only (pll enabled) notes: 1. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. only the falling edge of lale matters with respect to the specification . 2. in pll bypass mode, lclk[n] is the inverted version of the internal clock with the delay of tlbkhkt. in this mode, signals are latched at the raising edge of the internal clock and are captured at falling edge of the internal clock. lsync_in output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov1 t lbkhov2 t lbkhov3 input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh1 t lbivkh1 t lbivkh2 t lbixkh2 t lbkhox1 t lbkhoz1 t lbkhox2 t lbkhoz2 input signal: lgta t lbotot t lbkhoz2 t lbkhox2 t lbkhov4
44 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 11-3. local bus signals (pll bypass mode) output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbklov2 lclk[n] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkh2 t lbivkh2 t lbklox1 t lbkloz2 t lbotot internal launch/capture clock t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbkhkt t lbklov4
45 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] table 11-3 describes the general timing parameters of the local bus interface at v dd = 3.3v dc with pll disabled. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to local bus clock for pll bypass mode. timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which preceeds lclk by t lbkhkt . 3. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between comple- mentary signals at bv dd /2. 4. all signals are measured from bv dd /2 of the rising edge of local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3v signaling levels. 5. input timings are measured at the pin. 6. the value of t lbotot is the measurement of the minimum time between the negation of lale and any change in lad. 7. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. guaranteed by characterization. table 11-3. local bus general timing parameters: pll bypassed parameter symbol (1) min max unit notes local bus cycle time t lbk 12 ? ns (2) local bus duty cycle t lbkh /t lbk 45 55 % internal launch/capture clock to lclk delay t lbkhkt 2.3 3.9 ns (8) input setup to local bus clock (except lupwait) t lbivkh1 5.7 ? ps (4)(5) lupwait input setup to local bus clock t lbivkh2 5.6 ? ns (4)(5) input hold from local bus clock (except lupwait) t lbixkh1 -1.8 ? ns (4)(5) lupwait input hold from local bus clock t lbixkh2 -1.3 ? ns (4)(5) lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns (4)(5) local bus clock to output valid (except lad/ldp and lale) t lbklov1 ? -0.3 ns (6) local bus clock to data valid for lad/ldp t lbklov2 ? -0.1 ns local bus clock to address valid for lad t lbklov3 ? 0ns (4) local bus clock to lale assertion t lbklov4 ? 0ns (4) output hold from local bus clock (except lad/ldp and lale) t lbklox1 -3.2 ? ns (4) output hold from local bus clock for lad/ldp t lbklox2 -3.2 ? ns (4) local bus clock to output high impedance (except lad/ldp and lale) t lbkloz1 ? 0.2 ns (7) local bus clock to output high impedance for lad/ldp t lbkloz2 ? 0.2 ns (7)
46 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 11-4. local bus signals, gpcm/upm signals for lccr[clkdiv] = 2 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1
47 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 11-5. local bus signals, gpcm/upm signals for lccr[clkdiv] = 2 (pll bypass mode) internal launch/capture clock upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 (pll bypass mode) lclk t lbklox1 t lbivkh2 t lbixkh2 t lbivkh1 t lbixkh1
48 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 11-6. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4 input signals: lad[0:31]/ldp[0:3]
49 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 11-7. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (pll bypass mode) internal launch/capture clock upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] (pll bypass mode) lclk t lbklov1 t lbkloz1 t lbklox1 t lbivkh2 t lbixkh2 t lbivkh1 t lbixkh1
50 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 12. jtag this section describes the ac elec trical specificat ions for the ieee 1149.1 (j tag) interface of the pc8641. 12.1 jtag dc electrical characteristics table 12-1 provides the dc electrical characteristics for the jtag interface. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 6 and table 3-2 on page 7 . table 12-2 provides the jtag ac timing specifications as defined in figure 12-2 on page 51 through figure 12-4 on page 52 . table 12-1. jtag dc electrical characteristics parameter symbol (1) min max unit high-level input voltage v ih 2ov dd + 0.3v v low-level input voltage v il -0.3 0.8 v input current (v in (1) = 0v or v in = v dd ) i in ?5a high-level output voltage (ov dd = min, i oh = -100 a) v oh ov dd - 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ?0.2v table 12-2. jtag ac timing specificatio ns (independent of sysclk) (1) (at recommended operating conditions (see table 3-2 on page 7 ) parameter symbol (2) min max unit notes jtag external clock frequency of operation f jtg 033.3mhz jtag external clock cycle time t jtg 30 ? ns jtag external clock pulse width measured at 1.4v t jtkhkl 15 ? ns jtag external clock rise and fall times t jtgr & t jtgf 02ns (6) trst assert time t trst 25 ? ns (3) input setup times: - boundary-scan data - tms, tdi t jtdvkh t jtivkh 15 0 ? ? ns (4) input hold times: - boundary-scan data - tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns (4)
51 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] notes: 1. all outputs are measured from the mid point voltage of the falling/rising edge of t tclk to the midpoint of t he signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50 load (see figure 12-1 ). time- of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design. figure 12-1 provides the ac test load for tdo and the boundary-scan outputs. figure 12-1. ac test load for the jtag interface figure 12-2 provides the jtag clock input timing diagram. figure 12-2. jtag clock input timing diagram note: vm = midpoint voltage (ov dd /2). valid times: - boundary-scan data - tdo t jtkldv t jtklov 4 4 20 25 ns (5) output hold times: - boundary-scan data - tdo t jtkldx t jtklox 30 30 ? ? ns (5) jtag external clock to output high impedance: - boundary-scan data - tdo t jtkldz t jtkloz 3 3 19 9 ns (5)(6) table 12-2. jtag ac timing specificatio ns (independent of sysclk) (1) (at recommended operating conditions (see table 3-2 on page 7 ) (continued) parameter symbol (2) min max unit notes ov dd /2 output z 0 = 50 r l = 50 vm vm vm t jtg t jtgr t jtgf t jtkhkl jtag external clock
52 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 12-3 provides the trst timing diagram. figure 12-3. trst timing diagram note: vm = midpoint voltage (ov dd /2). figure 12-4 provides the boundary-scan timing diagram. figure 12-4. boundary-scan timing diagram note: vm = midpoint voltage (ov dd /2). 13. i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the pc8641. 13.1 i 2 c dc electrical characteristics table 13-1 provides the dc electrical characteristics for the i 2 c interfaces. notes: 1. output voltage (open drain or open co llector) condition = 3 ma sink current. 2. refer to the pc8641 powerquicc iii integrated host processor reference manual for information on the digital filter used. 3. i/o pins will obstruct the sda and scl lines if ov dd is switched off. trst t trst vm vm vm jtag external clock boundary data inputs boundary data outputs boundary data outputs t jtdxkh t jtdvkh t jtkldv t jtkldz output data valid t jtkldx vm input data valid output data valid table 13-1. i 2 c dc electrical characteristics (at recommended operating conditions with ov dd of 3.3v 5%) parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v input low voltage level v il -0.3 0.3 ov dd v low level output voltage v ol 0 0.2 ov dd v (1) pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns (2) input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i -10 10 a (3) capacitance for each i/o pin c i ?10pf
53 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 13.2 i 2 c ac electrical specifications table 13-2 provides the ac timing parameters for the i 2 c interfaces. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c tim- ing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp ri- ate letter: r (rise) or f (fall). 2. as a transmitter, the pc8641 provides a delay time of at leas t 300 ns for the sda signal (referred to the vihmin of the scl signal) to bridge the undefined region of the falling edge of scl to avoid unintended generation of start or stop condition. when pc8641 acts as the i 2 c bus master while transmitting, pc8641 drives both scl and sda. as long as the load on scl and sda are balanced, pc8641 would not cause unintended genera tion of start or stop condition. therefore, the 300 ns sda output delay time is not a concern. if, under some rare condition, the 300 ns sda output delay time is required for pc8641 as transmitter, the following setting is recommended for the fdr bit field of the i2cfdr register to ensure both the desired i 2 c scl clock frequency and sda output delay time are achieved, assuming that the desired i 2 c scl clock fre- quency is 400 khz and the digital filter sampling rate register (i2cdfsrr) is programmed wit h its default setting of 0x10 (decimal 16): i 2 c source clock frequency 333 mhz 266 mhz 200 mhz 133 mhz fdr bit setting 0x2a 0x05 0x26 0x00 actual fdr divider selected 896 704 512 384 actual i 2 c scl frequency generated 371 khz 378 khz 390 khz 346 khz for the detail of i 2 c frequency calculation, refer to the application note an2919 ?determining the i 2 c frequency divider ratio for scl?. note that the i 2 c source clock frequency is half of the mpx clock frequency for pc8641. 3. the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. guaranteed by design. table 13-2. i 2 c ac electrical specificati ons (all values refer to v ih (min) and v il (max) levels (see table 13-1 on page 52 ) parameter symbol (1) min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl (4) 1.3 ? s high period of the scl clock t i2ch (4) 0.6 ? s setup time for a repeated start condition t i2svkh (4) 0.6 ? s hold time (repeated) start condition (a fter this period, the first clock pulse is generated) t i2sxkl (4) 0.6 ? s data setup time t i2dvkh (4) 100 ? ns data input hold time: - cbus compatible masters - i 2 c bus devices t i2dxkl ? 0 (2) ? ? s data output delay time t i2ovkl ?0.9 (3) s set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd v
54 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 13-1 provides the ac test load for the i 2 c. figure 13-1. i 2 c ac test load figure 13-2 shows the ac timing diagram for the i 2 c bus. figure 13-2. i 2 c bus ac timing diagram 14. high-speed interfaces this section describes the common dc electrical specifications for the high-speed interconnect inter- faces (serial rapidio and pci express) of the pc8641. 14.1 dc requirements for se rdes reference clocks the serdes reference clocks are sd1_ref_clk, sd1_ref_clk , sd2_ref_clk and sd2_ref_clk . ? recommended minimum operating voltage is -0.4v; recommended maximum operating voltage is 1.32v; maximum absolute voltage is 1.72v. ? each differential clock input has an internal 50 termination to gnd. the reference clock must be able to drive this termination. the input is ac-coupled on chip following the termination. ? the amplitude of the clock must be at least a 400-mv differential peak-peak for single-ended clock. if driven differentially, each signal wire needs to drive 100 mv around common mode voltage. ? the differential reference clock (sd n _ref_clk/sd n _ref_clk ) input is hcsl compatible dc coupled or lvds compatible with ac coupling. ov dd /2 output z 0 = 50 r l = 50 sr s sda scl t i2cf t i2cl t i2sxkl t i2dxkl t i2dvkh t i2ch t i2sxkl ps t i2cf t i2cr t i2pvkh t i2svkh t i2khkl
55 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 14-1. driver and receiver of serdes (p ci express, serial rapidio, and sd n _ref_clk/sd n _ref_clk 15. pci express this section describes the dc and ac electrical s pecifications for the pci express bus of the pc8641. 15.1 dc requirements for pci express sd n _ref_clk and sd n _ref_clk for more information, see section 14.1 ?dc requirements for serdes reference clocks? on page 54 . 15.2 ac requirements for pci express serdes clocks table 15-1 lists ac requirements. 15.3 clocking dependencies the ports on the two ends of a link must transmit data at a rate that is within 60 0 parts per million (ppm) of each other at all times. this is specified to allow bit rate clock sources with a 300 ppm tolerance. 15.4 physical layer specifications the following is a summary of the specifications for the physical layer of pci express on this device. for further details as well as the specifications of t he transport and data link layer please use the pci express base specification. rev. 1.0a document. output driver 50 50 serial data out input amp serial data in 50 50 table 15-1. sd n _ref_clk and sd n _ref_clk ac requirements symbol parameter description min typical max units notes t ref refclk cycle time ? 10 ? ns ? t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ??100ps? t refpj phase jitter. deviation edge location in edge location with respect to mean - 50 ?50ps?
56 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 15.4.1 differential transmitter (tx) output table 15-2 defines the specifications for the differential output at all transmitters (txs). the parameters are specified at the component pins. table 15-2. differential transmitter (t x) output specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note (1) . v tx-diffp-p differential peak-to-peak output voltage 0.8 1.2 v v tx-diffp-p = 2*|v tx-d+ - v tx-d- | see note (2) . v tx-de-ratio de- emphasized differential output voltage (ratio) -3.0 -3.5 -4.0 db ratio of the v tx-diffp-p of the second and following bits after a transition divided by the vtx-diffp-p of the first bit after a transition. see note (2) . t tx-eye minimum tx eye width 0.70 ui the maximum transmitter jitter can be derived as t tx-max- jitter = 1 - t tx-eye = 0.3 ui. see notes (2) and (3) . t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median. 0.15 ui jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes (2) and (3) . t tx-rise, ttx-fall d+/d- tx output rise/fall time 0.125 ui see notes (2) and (4) v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-acp = rms(|v txd+ - v txd -|/2 -v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ - v tx-d- |/2 see note (2) v tx-cm-dc-active- idle-delta absolute delta of dc common mode voltage during lo and electrical idle 0 100 mv | vtx-cm-dc (during lo) - v tx-cm-idle-dc (during electrical idle) |<=100 mv v tx-cm-dc = dc (avg) of |v tx-d+ - v tx-d- |/2 [lo] v tx-cm-idle-dc = dc (avg) of |v tx-d+ - v tx-d- |/2 [electrical idle] see note (2) . v tx-cm-dc-line- delta absolute delta of dc common mode between d+ and d? 025mv | vtx-cm-dc-d+ - v tx-cm-dc-d- | <= 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d- = dc (avg) of |v tx-d- | see note (2) . v tx-idle-diffp electrical idle differential peak output voltage 020mv v tx-idle-diffp = |v tx-idle-d+ -v tx-idle-d- | <= 20 mv see note (2) . v tx-rcv-detect the amount of voltage change allowed during receiver detection 600 mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. see note (5) . v tx-dc-cm the tx dc common mode voltage 03.6v the allowed dc common mode voltage under any conditions. see note (5) . i tx-short tx short circuit current limit 90 ma the total current the transmitter can provide when shorted to its ground. t tx-idle-min minimum time spent in electrical idle 50 ui minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit after successfully receiv ing an electrical idle ordered set.
57 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timi ng and voltage compliance test load as shown in figure 15-3 on page 61 and measured over any 250 consecutive tx uis. (also re fer to the transmitter compliance eye diagram shown in figure 15-1 on page 58 .) 3. a t tx-eye = 0.70 ui provides for a total sum of dete rministic and random jitter budget of t tx-jitter-max = 0.30 ui for the trans- mitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted t hat the median is not the sa me as the mean. the jitter median describes the point in time where th e number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. th is input impedance requirement applies to all valid input levels. the referenc e impedance for return loss measurements is 50 to ground for both the d+ and d- line (that is, as measured by a vector network analyzer with 50 probes; see figure 15-3 on page 61 ). note that the series capacitors c tx is optional for the return loss measurement. 5. measured between 20-80% at transmitter package pins into a test load as shown in figure 15-3 for both v tx-d+ and v tx-d- . 6. see section 4.3.1.8 of the pci expr ess base specifications rev 1.0a. 7. see section 4.2.6.3 of the pci expr ess base specifications rev 1.0a. 8. pc8641d serdes transmitter does not have c tx built-in. an external ac coupling capacitor is required. t tx-idle-set-to- idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set 20 ui after sending an electrical id le ordered set, the transmitter must meet all electrical idle sp ecifications within this time. this is considered a debounce ti me for the transmitter to meet electrical idle afte r transitioning from lo. t tx-idle-to-diff- data maximum time to transition to valid tx specifications after leaving an electrical idle condition 20 ui maximum time to meet all tx specifications when transitioning from elec trical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications after leaving electrical idle. rl tx-diff differential return loss 12 db measured over 50 mhz to 1.25 ghz. see note (4) rl tx-cm common mode return loss 6 db measured over 50 mhz to 1.25 ghz. see note (3) z tx-diff-dc dc differential tx impedance 80 100 120 tx dc differential mode low impedance. z tx-dc transmitter dc impedance 40 required tx d+ as wellall states. l tx-skew lane-to-lane output skew 500 + 2 ui ps static skew between any two transmitter lanes within a single link. c tx ac coupling capacitor 75 200 nf all transmitters shall be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. see note (8) t crosslink crosslink random timeout 01ms this random timeout helps reso lve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. see note (7) . table 15-2. differential transmitter (tx) outp ut specifications (continued) symbol parameter min nom max units comments
58 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 15.4.2 transmitter comp liance eye diagrams the tx eye diagram in figure 15-1 is specified using the passive compliance/test measurement load (see figure 15-3 on page 61 ) in place of any real pci express interconnect + rx component. there are two eye diagrams that must be met for the transmitter. both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note: it is recommended that the recovered tx ui is ca lculated using all edges in the 3500 consecutive ui inter- val with a fit algorithm using a minimization merit function (i.e., least squares and median deviation fits). figure 15-1. minimum transmitter timing and voltage output compliance specifications v rx-diff = 0 mv (d+ d- crossing point) v rx-diff = 0 mv (d+ d- crossing point) (transition bit) v tx-diffp-p-min = 800 mv (de-emphasized bit) 566 mv (3 db) >= v tx-diffp-p-min >= 505 mv (4 db) .07 ui = ui - 0.3 ui(j tx-total-max ) (transition bit) v tx-diffp-p-min = 800 mv
59 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 15.4.3 differential receiver (rx) input specifications table 15-3 defines the specifications for the differential i nput at all receivers (rxs). the parameters are specified at the component pins. table 15-3. differential receiver (r x) input specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note (1) . v rx-diffp-p differential peak-to-peak output voltage 0.175 1.200 v v rx-diffp-p = 2*|v rx-d+ - v rx-d- | see note (2) . t rx-eye minimum receiver eye width 0.4 ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 - t rx-eye = 0.6 ui. see notes (2) and (3) . t rx-eye-median-to-max -jitter maximum time between the jitter median and maximum deviation from the median 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes (2)(3)(7) . v rx-cm-acp ac peak common mode input voltage 150 mv v rx-cm-acp = |v rxd+ - v rxd- |/2 - v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ - v rx-d- |/2 see note (2) rl rx-diff differential return loss 15 db measured over 50 mhz to 1.25 ghz with the d+ and d-lines biased at +300 mv and -300 mv, respectively. see note (4) rl rx-cm common mode return loss 6db measured over 50 mhz to 1.25 ghz with the d+ and d-lines biased at 0v. see note (4) z rx-diff-dc dc differential input impedance 80 100 120 rx dc differential (5) z rx-dc dc input impedance 40 50 60 required rx d+ as well as d-dc impedance (50 20% tolerance). see notes (2) and (5) z rx-high-imp-dc powered down dc input impedance 200 k required rx d+ as well as d-dc impedance when the receiver terminations do not have power. see note (6) v rx-idle-det-diffp-p electrical idle detect threshold 65 175 mv v rx-idle-det-diffp-p = 2*|v rx-d+ -v rx-d- | measured at the package pins of the receiver t rx-idle-det-diff-entertime unexpected electrical idle enter detect threshold integration time 10 ms an unexpected electrical idle (v rx-diffp-p < v rx-idle-det-diffp-p ) must be recognized no longer than t rx-idle-det-diff-entering to signal an unexpected idle condition. l tx-skew total skew 20 ns skew across all lanes on a link. this includes variation in the length of skp ordered set (e.g. com and one to five symbols) at the rx as well as any delay differences arising from the interconnect itself.
60 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement poi nt and measured over any 250 c onsecutive uis. the test load in figure 15-3 on page 61 should be used as the rx device when taking measurements (a lso refer to the receiver compliance eye diagram shown in figure 15-2 on page 61 ). if the clocks to the rx and tx are not derived fr om the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui determinis tic and random jitter budget for the transmitter and inter- connect collected any 250 consecutive uis. the trx-eye- median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget col - lected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the aver- aged time value. if the clocks to the rx and tx are not deriv ed from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4. the receiver input impedance shall result in a differential re turn loss greater than or equal to 15 db with the d+ line biase d to 300 mv and the d- line biased to -300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requ irement applies to all valid input levels. the reference impedance for return loss measurements for is 50 to ground for both the d+ and d- line (that is, as mea- sured by a vector network analyzer with 50 probes - see figure 15-3 ). note: that the series c apacitors ctx is optional for the return loss measurement. 5. impedance during all ltssm states. when transitioning from a fundamental reset to detect (t he initial state of the ltssm) there is a 5 ms transition time before receiver terminatio n values must be met on all un-configured lanes of a port. 6. the rx dc common mode impedance that exists when no power is present or fundamental re set is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7. it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algo- rithm using a minimization merit function. least squares and me dian deviation fits have worked well with experimental and simulated data. 15.5 receiver compli ance eye diagrams the rx eye diagram in figure 15-2 is specified using the passive compliance/test measurement load (see figure 15-3 ) in place of any real pci express rx component. note: in general, the minimum receiver eye diagram measured with the compliance/test measurement load (see figure 15-3 ) will be larger than t he minimum receiver eye diagram measured over a range of systems at the input receiver of any real pci express component. the degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real pci express component to vary in impedance from the co mpliance/test measurement load. the input receiver eye diagram is implementation specific and is not sp ecified. rx component designer should provide addi- tional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in figure 15-2 ) expected at the input receiver based on some adequate combination of system simulations and the return loss measured looking into the rx package and silicon. the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note: the reference impedance for return loss measurements is 50 to ground for both the d+ and d- line (i.e., as measured by a vector network analyzer with 50 probes; see figure 15-3 ). note that the series capac- itors, ctx, are optional fo r the return loss measurement.
61 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 15-2. minimum receiver eye timing and voltage compliance specification 15.5.1 compliance test and measurement load the ac timing and voltage parameters must be verifi ed at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 15-3 . note: the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowl- edge that package/board routing may benefit from d+ and d? not being exactly matched in length at the package pin boundary. figure 15-3. compliance test/measurement load 16. serial rapidio this section describes the dc and ac electrical sp ecifications for the rapidio interface of the pc8641, for the lp-serial physical layer. the electrical spec ifications cover both sing le and multiple-lane links. two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 gbaud. two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to driving two connectors across a backp lane. a single receiver specificat ion is given that will accept sig- nals from both the short run and long run transmitter specifications. the short run transmitter should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector. this co vers the case where connections are made to a mez- zanine (daughter) card. the minimum swings of the short run specification reduce the overall power used by the transceivers. v rx-diff = 0 mv (d+ d- crossing point) v rx-diff = 0 mv (d+ d- crossing point) 0.4 ui = t rx-eye-min v rx-diffp-p- min > 175 mv d+ package pin d- package pin tx silicon + package r = 50 r = 50 c = c tx c = c tx
62 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 the long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. this allows a user to drive signals across two connectors and a backplane. the specifications allow a distance of at least 50 cm at all baud rates. all unit intervals are specified with a tolerance of 100 ppm. the worst case frequency difference between any transmit and re ceive clock will be 200 ppm. to ensure interoperability between drivers and receivers of differ ent vendors and technologies, ac cou- pling at the receiver input must be used. 16.1 dc requirements for serial rapidio sd n _ref_clk and sd n _ref_clk for more information, see section 14.1 ?dc requirements for serdes reference clocks? on page 54 . 16.2 ac requirements for serial rapidio sd n _ref_clk and sd n _ref_clk table 16-1 lists ac requirements. 16.3 signal definitions lp-serial links use differential signaling. this section defines terms used in the description and specification of differential signals. figure 16-1 on page 63 shows how the signals are defined. the figures show waveforms for either a transmitter output (td and td ) or a receiver input (rd and rd ). each signal swings between a volts and b volts wher e a > b. using these waveforms, the definitions are as follows: 1. the transmitter output signals and the receiver input signals td, td , rd and rd each have a peak-to-peak swing of a - b volts. 2. the differential output signal of the transmitter, v od , is defined as v td -v td 3. the differential input signal of the receiver, v id , is defined as v rd -v rd 4. the differential output signal of the transmitter and the differential input signal of the receiver each range from a - b to -(a - b) volts. 5. the peak value of the differential transmitter out put signal and the differential receiver input sig- nal is a - b volts. 6. the peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 * (a - b) volts. table 16-1. sd n _ref_clk and sd n _ref_clk ac requirements symbol parameter description mi n typical max units comments t ref refclk cycle time ? 10(8) ? ns 8 ns applies only to serial rapidio with 125-mhz reference clock t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ?? 80 ps ? t refpj phase jitter. deviation in edge location with respect to mean edge location - 40 ? 40 ps
63 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 16-1. differential peak-peak voltage of transmitter or receiver to illustrate these definitions using real values, consider th e case of a cml (current mode logic) trans- mitter that has a common mode voltage of 2.25v and each of its outputs, td and td, has a swing that goes between 2.5v and 2.0v. usin g these values, the peak-to-peak voltage swing of the signals td and td is 500 mv p-p. the differential output signal ranges between 500 mv and ?500 mv. the peak differ- ential voltage is 500 mv. the peak-to-peak differential voltage is 1000 mv p-p. 16.4 equalization with the use of high speed serial links, the inte rconnect media will caus e degradation of th e signal at the receiver. effects such as inter-symbol interference (i si) or data dependent jitter are produced. this loss can be large enough to degrade the eye opening at t he receiver beyond what is allowed in the specification. to negate a portion of these effects, equalization can be used. the most common equalization tech- niques that can be used are: ? a passive high pass filter network placed at the receiver. this is often referred to as passive equalization. ? the use of active circuits in the receiver. this is often referred to as adaptive equalization. 16.5 explanatory note on tran smitter and receiver specifications ac electrical specifications are given for transmitte r and receiver. long run and short run interfaces at three baud rates (a total of six cases) are described. the parameters for the ac electrical specifications ar e guided by the xaui electrical interface specified in clause 47 of ieee 802.3ae-2002. xaui has similar application goals to serial rapidio, as described in section 9.1 on page 26 . the goal of this standard is that electrical designs for serial ra pidio can reuse electrical designs for xaui, suitably modified for applications at the baud intervals and reaches described herein. a volts b volts td or rd td or rd differential peak-peak = 2*(a-b)
64 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 16.6 transmitter specifications lp-serial transmitter electrical and timing specifications are stated in the text and tables of this section. the differential return loss, s11, of the transmitter in each case shall be better than ? -10 db for (baud frequency)/10 < freq(f) < 625 mhz, and ? -10 db + 10log(f/625 mhz) db for 625 mhz freq(f) baud frequency the reference impedance for the differential return loss measurements is 100 ohm resistive. differential return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. the output impedance requirement applies to all valid output levels. it is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter out- put, in each case have a minimum value 60 ps. it is recommended that the timing skew at the output of an lp-serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 gb, 20 ps at 2.50 gb and 15 ps at 3.125 gb. table 16-2. short run transmitter ac timing specifications: 1.25 gbaud characteristic symbol range unit notes min max output voltage v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps 100 ppm table 16-3. short run transmitter ac timing specifications: 2.5 gbaud characteristic symbol range unit notes min max output voltage, v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps 100 ppm
65 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] table 16-4. short run transmitter ac timing specifications: 3.125 gbaud characteristic symbol range unit notes min max output voltage v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps 100 ppm table 16-5. long run transmitter ac timing specifications: 1.25 gbaud characteristic symbol range unit notes min max output voltage v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps 100 ppm table 16-6. long run transmitter ac timing specifications: 2.5 gbaud characteristic symbol range unit notes min max output voltage v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps 100 ppm
66 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 for each baud rate at which an lp-serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown in figure 16-2 with the parameters specified in table 16-8 on page 67 when measured at the out- put pins of the device and the device is driving a 100 ohm 5% differential resistive load. the output eye pattern of an lp-serial transmitter that implements pre-emphasis (to equalize the link and reduce inter- symbol interference) need only comply with the transmitter output compliance mask when pre-empha- sis is disabled or minimized. figure 16-2. transmitter output compliance mask table 16-7. long run transmitter ac timing specifications: 3.125 gbaud characteristic symbol range unit notes min max output voltage v o -0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p deterministic jitter j d 0.17 ui p-p total jitter j t 0.35 ui p-p multiple output skew s mo 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps 100 ppm 0 time in ui 0 1 a b 1-b 1-a transmitter differential output voltage v diff max -v diff max -v diff min v diff min
67 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 16.7 receiver s pecifications lp-serial receiver electrical and timing specifications are stated in the text and tables of this section. receiver input impedance shall result in a differential return loss better that 10 db and a common mode return loss better than 6 db from 100 mhz to (0.8)*(baud frequency). this includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. ac coupling components are included in this requirement. the reference impedance for return loss measurements is 100 resistive for differential return loss and 25 resistive for common mode. note: 1. total jitter is composed of three components, determinist ic jitter, random jitter and single frequency sinusoidal jitter . the sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 16-3 on page 69 . the sinusoidal jit- ter component is included to ensure margin for low frequen cy jitter, wander, noise, crosstalk and other variable system effects. table 16-8. transmitter differential output eye diagram parameters transmitter type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud short range 250 500 0.175 0.39 1.25 gbaud long range 400 800 0.175 0.39 2.5 gbaud short range 250 500 0.175 0.39 2.5 gbaud long range 400 800 0.175 0.39 3.125 gbaud short range 250 500 0.175 0.39 3.125 gbaud long range 400 800 0.175 0.39 table 16-9. receiver ac timing spec ifications ? 1.25 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ui p-p measured at receiver total jitter tolerance (1) j t 0.65 ui p-p measured at receiver multiple input skew s mi 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber 10 ?12 unit interval ui 800 800 ps 100 ppm
68 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 note: total jitter is composed of three components, determinis tic jitter, random jitter and single frequency sinusoidal jitter. the sinuso- idal jitter may have any amplitude and frequency in the unshaded region of figure 16-3 on page 69 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. note: 1. total jitter is composed of three components, determinist ic jitter, random jitter and single frequency sinusoidal jitter . the sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 16-3 . the sinusoidal jitter compo- nent is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects table 16-10. receiver ac timing s pecifications: 2.5 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ui p-p measured at receiver total jitter tolerance (1) j t 0.65 ui p-p measured at receiver multiple input skew s mi 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber 10 ?12 unit interval ui 400 400 ps 100 ppm table 16-11. receiver ac timing specifications: 3.125 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ui p-p measured at receiver total jitter tolerance (1) j t 0.65 ui p-p measured at receiver multiple input skew s mi 22 ns skew at the receiver input between lanes of a multilane link bit error rate ber 10 ?12 unit interval ui 320 320 ps 100 ppm
69 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 16-3. single frequency sinusoidal jitter limits 16.8 receiver eye diagrams for each baud rate at which an lp-serial receiver is specified to operate, the receiver shall meet the cor- responding bit error rate specification ( table 16-9 on page 67 , table 16-10 on page 68 , table 16-11 on page 68 ) when the eye pattern of the receiver test signa l (exclusive of sinusoi dal jitter) falls entirely within the unshaded portion of the rece iver input compliance mask shown in figure 16-4 on page 70 with the parameters specified in table 16-12 on page 70 . the eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 5% differential resistive load. frequency 22.1 khz 1.875 mhz 20 mhz sinuso?dal jitter amplitude 8.5 ui p-p 0.10 ui p-p
70 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 16-4. receiver input compliance mask table 16-12. receiver input compliance mask parame ters exclusive of sinusoidal jitter receiver type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud 100 800 0.275 0.400 2.5 gbaud 100 800 0.275 0.400 3.125 gbaud 100 800 0.275 0.400 1 0 0 a b 1-b 1-a time in ui receiver differential input voltage v diff max -v diff max -v diff min v diff min
71 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 16.9 measurement and test requirements since the lp-serial electrical specification are guided by the xaui electrical in terface specified in clause 47 of ieee 802.3ae-2002, the measurement and test requirements defined here are similarly guided by clause 47. in addition, the cjpat test pattern defined in annex 48a of ie ee802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter measurements . annex 48b of ieee802.3ae-2002 is recommended as a reference for additional information on jitter test methods. 16.9.1 eye template measurements for the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 db point at (baud frequency)/1667 is applied to the jitter. the data pattern for template measurements is the continuous jitter test pattern (cjpat) defined in annex 48a of ieee802.3ae. all lanes of the lp- serial link shall be active in both the transmit and re ceive directions, and opposite ends of the links shall use asynchronous clocks. four lane implementation s shall use cjpat as defined in annex 48a. single lane implementations shall use the cjpat sequence specified in annex 48a for transmission on lane 0. the amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10 -12 . the eye pattern shall be measured with ac coupling and the compliance template centered at 0 volts differential. the left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. the load for this test sh all be 100 ohms resistive 5% differential to 2.5 ghz. 16.9.2 jitter test measurements for the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 db point at (baud frequency)/1667 is applied to the jitter. the data pattern for jitter measurements is the continu- ous jitter test pattern (cjpat) patt ern defined in annex 48a of ieee802 .3ae. all lanes of the lp-serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. four lane implementations shall use cjpat as defined in annex 48a. single lane implementations shall use the cjpat sequence specifi ed in annex 48a for transmission on lane 0. jitter shall be measured with ac coupling and at 0 volts differential. jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test procedure resulting in a ber curve such as that described in annex 48b of ieee802.3ae. 16.9.3 transmit jitter transmit jitter is measured at the driver output w hen terminated into a load of 100 ohms resistive 5% differential to 2.5 ghz. 16.9.4 jitter tolerance jitter tolerance is measured at the receiver using a jitter tolerance test signal. this signal is obtained by first producing the sum of deterministic and random jitter defined in section 8.6 and then adjusting the signal amplitude until the data eye contacts the 6 po ints of the minimum eye opening of the receive tem- plate. note that for this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (includi ng jitter) about the mean zero crossing. eye tem- plate measurement requirements are as defined above. random jitter is calibrated using a high pass filter with a low frequency corner at 20 mhz and a 20 db/decade roll-off below this. the required sinuso- idal jitter specified in section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
72 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 17. package this section details package parameters and dimensions. 17.1 package parameters for the pc8641 the package parameters are as provided in the following list. the package type is 33 mm x 33 mm, 1023 pins. there are two package options: high-lead flip chip-ceramic ball grid array (fc-cbga), and lead- free (fc-cbga). for all package types: die size 12.4 mm x 15.3 mm package outline 33 mm x 33 mm interconnects 1023 pitch 1 mm total capacitor count 43 caps; 100 nf each for high-lead fc-cbga (package option: hcte (1) gh) maximum module height 2.97 mm minimum module height 2.47 mm solder balls 89.5% pb 10.5% sn ball diameter (typical (2) )0.60 mm for rohs lead-free fc-cbga (package option: hitce sh) maximum module height 2.72 mm minimum module height 2.27 mm solder balls 95.5% sn 4.0% ag 0.5% cu ball diameter (typical (2) )0.60 mm notes: 1. high-coefficient of thermal expansion. 2. typical ball diameter is before reflow.
73 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 17.2 mechanical dimensions of the pc8641 fc-cbga the mechanical dimensions and bottom surface nomenclature of the pc8641d (dual core) and pc8641 (single core) high-lead fc-cbga (package option: hcte hx) and lead-free fc-cbga (package option: hcte sh) are shown respectfully in table 17-1 and table 17-2 on page 74 . figure 17-1. pc8641 high-head fc-cbga dimensions notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. seating plane side view bottom view top view 2.97 max 0.75 0.55 1.32 1.1 0.9 0.82 4x 0.6 max 2x 10.7 min 4x 14 max a1 index
74 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. capacitors may not be present on all devices. 6. caution must be taken not to short capacitors or expose metal capacitor pads on package top. 7. all dimensions symmetrical about centerlines unless otherwise specified. 8. note that for pc8641 (single core) the solder balls for the following signals/pins are not populated in the package: vdd_core1 (r16, r18, r20, t17, t19, t21, t23, u16, u18, u22, v17, v19, v21, v23, w16, w18, w20, w22, y17, y19, y21, y23, aa16, aa18, aa20, aa22, ab23, ac24) and sensevdd_core1 (u20). figure 17-2. pc8641d lead-free fc-cbga dimensions bottom view side view top view seating plane
75 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. capacitors may not be present on all devices. 6. caution must be taken not to short capacitors or expose metal capacitor pads on package top. 7. all dimensions symmetrical about centerlines unless otherwise specified. 8. note that for pc8641 (single core) the solder balls for the following signals/pins are not populated in the package: vdd_core1 (r16, r18, r20, t17, t19, t21, t23, u16, u18, u22, v17, v19, v21, v23, w16, w18, w20, w22, y17, y19, y21, y23, aa16, aa18, aa20, aa22, ab23, ac24) and sensevdd_core1 (u20). 18. signal listings table 18-1 provides the pin assignments for the signals. notes for the signal changes on the single core device (pc8641) are italized and prefixed by ?s?. table 18-1. pc8641 signal reference by functional block name (1) package pin number pin type power supply notes ddr memory interface 1 signals (2)(3) d1_mdq[0:63] d15, a14, b12, d12, a15, b15, b13, c13, c11, d11, d9, a8, a12, a11, a9, b9, f11, g12, k11, k12, e10, e9, j11, j10, g8, h10, l9, l7, f10, g9, k9, k8, ac6, ac7, ag8, ah9, ab6, ab8, ae9, af9, al8, am8, am10, ak11, ah8, ak8, aj10, ak10, al12, aj12, al14, am14, al11, am11, am13, ak14, am15, aj16, ak18, al18, aj15, al15, al17, am17 i/o d1_gv dd d1_mecc[0:7] m8, m7, r8, t10, l11, l10, p9, r10 i/o d1_gv dd d1_mdm[0:8] c14, a10, g11, h9, ad7, aj9, am12, ak16, n10 o d1_gv dd d1_mdqs[0:8] a13, c10, h12, j7, ae8, am9, ak13, ak17, n9 i/o d1_gv dd d1_mdqs [0:8] d14, b10, h13, j8, ad8, al9, aj13, am16, p10 i/o d1_gv dd d1_mba[0:2] aa8, aa10, t9 o d1_gv dd d1_ma[0:15] y10, w8, w9, v7, v8, u6, v10, u9, u7, u10, y9, t6, t8, ae12, r7, p6 o d1_gv dd d1_mwe ab11 o d1_gv dd d1_mras ab12 o d1_gv dd d1_mcas ac10 o d1_gv dd d1_mcs [0:3] ab9, ad10, ac12, ad11 o d1_gv dd d1_mcke[0:3] p7, m10, n8, m11 o d1_gv dd (23) d1_mck[0:5] w6, e13, ah11, y7, f14, ag10 o d1_gv dd d1_mck [0:5] y6, e12, ah12, aa7, f13, ag11 o d1_gv dd d1_modt[0:3] ac9, af12, ae11, af10 o d1_gv dd d1_mdic[0:1] e15, g14 io d1_gv dd (27) d1_mv ref am18 ddr port 1 reference voltage d1_gv dd /2 (3) ddr memory interface 2 signals (2)(3)
76 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 d2_mdq[0:63] a7, b7, c5, d5, c8, d8, d6, a5, c4, a3, d3, d2, a4, b4, c2, c1, e3, e1, h4, g1, d1, e4, g3, g2, j4, j2, l1, l3, h3, h1, k1, l4, aa4, aa2, ad1, ad2, y1, aa1, ac1, ac3, ad5, ae1, ag1, ag2, ac4, ad4, af3, af4, ah3, aj1, am1, am3, ah1, ah2, al2, al3, ak5, al5, ak7, am7, ak4, am4, am6, aj7 i/o d2_gv dd d2_mecc[0:7] h6, j5, m5, m4, g6, h7, m2, m1 i/o d2_gv dd d2_mdm[0:8] c7, b3, f4, j1, ab1, ae2, ak1, am5, k6 o d2_gv dd d2_mdqs[0:8] b6, b1, f1, k2, ab3, af1, al1, al6, l6 i/o d2_gv dd d2_mdqs [0:8] a6, a2, f2, k3, ab2, ae3, ak2, aj6, k5 i/o d2_gv dd d2_mba[0:2] w5, v5, p3 o d2_gv dd d2_ma[0:15] w1, u4, u3, t1, t2, t3, t5, r2, r1, r5, v4, r4, p1, ah5, p4, n1 o d2_gv dd d2_mwe y4 o d2_gv dd d2_mras w3 o d2_gv dd d2_mcas ab5 o d2_gv dd d2_mcs [0:3] y3, af6, aa5, af7 o d2_gv dd d2_mcke[0:3] n6, n5, n2, n3 o d2_gv dd (23) d2_mck[0:5] u1, f5, aj3, v2, e7, ag4 o d2_gv dd d2_mck [0:5] v1, g5, aj4, w2, e6, ag5 o d2_gv dd d2_modt[0:3] ae6, ag7, ae5, ah6 o d2_gv dd d2_mdic[0:1] f8, f7 io d2_gv dd (27) d2_mv ref a18 ddr port 2 reference voltage d2_gv dd /2 (3) high speed i/o interface 1 (serdes 1) (4) sd1_tx[0:7] l26, m24, n26, p24, r26, t24, u26, v24 o sv dd sd1_tx [0:7] l27, m25, n27, p25, r27, t25, u27, v25 o sv dd sd1_rx[0:7] j32, k30, l32, m30, t30, u32, v30, w32 i sv dd sd1_rx [0:7] j31, k29, l31, m29, t29, u31, v29, w31 i sv dd sd1_ref_clk n32 isv dd sd1_ref_clk n31 isv dd sd1_imp_cal_tx y26 analog sv dd (19) sd1_imp_cal_rx j28 analog sv dd (30) sd1_pll_tpd u28 osv dd (13)(17) sd1_pll_tpa t28 analog sv dd (13)(18) sd1_dll_tpd n28 osv dd (13)(17) sd1_dll_tpa p31 analog sv dd (13)(18) high speed i/o interface 2 (serdes 2) (4) sd2_tx[0:3] y24, aa27, ab25, ac27 o sv dd sd2_tx[4:7] ae27, ag27, aj27, al27 o sv dd (34) sd2_tx [0:3] y25, aa28, ab26, ac28 o sv dd table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
77 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] sd2_tx [4:7] ae28, ag28, aj28, al28 o sv dd (34) sd2_rx[0:3] y30, aa32, ab30, ac32 i sv dd (32) sd2_rx[4:7] ah30, aj32, ak30, al32 i sv dd (32)(35) sd2_rx [0:3] y29, aa31, ab29, ac31 i sv dd sd2_rx [4:7] ah29, aj31, ak29, al31 i sv dd (35) sd2_ref_clk ae32 isv dd sd2_ref_clk ae31 isv dd sd2_imp_cal_tx am29 analog sv dd (19) sd2_imp_cal_rx aa26 analog sv dd (30) sd2_pll_tpd af29 osv dd (13)(17) sd2_pll_tpa af31 analog sv dd (13)(18) sd2_dll_tpd ad29 osv dd (13)(17) sd2_dll_tpa ad30 analog sv dd (13)(18) special connection requirement pins no connects k24, k25, p28, p29, w26, w27, ad25, ad26 ? ? (13) reserved h30, r32, v28, ag32 ? ? (14) reserved h29, r31, w28, ag31 ? ? (15) reserved ad24, ag26 ? ? (16) ethernet miscellaneous signals (5) ec1_gtx_clk125 al23 ilv dd (39) ec2_gtx_clk125 am23 itv dd (39) ec_mdc g31 oov dd ec_mdio g32 i/o ov dd etsec port 1 signals (5) tsec1_txd[0:7]/ gpout[0:7] af25, ac23,ag24, ag23, ae24, ae23, ae22, ad22 o lv dd (6)(10) tsec1_tx_en ab22 olv dd (36) tsec1_tx_er ah26 olv dd tsec1_tx_clk ac22 ilv dd (40) tsec1_gtx_clk ah25 olv dd tsec1_crs am24 i/o lv dd (37) tsec1_col am25 ilv dd tsec1_rxd[0:7]/ gpin[0:7] al25, al24, ak26, ak25, am26, af26, ah24, ag25 i lv dd (10) tsec1_rx_dv aj24 ilv dd tsec1_rx_er aj25 ilv dd tsec1_rx_clk ak24 ilv dd (40) etsec port 2 signals (5) table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
78 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 tsec2_txd[0:3]/ gpout[8:15] ab20, aj23, aj22, ad19 o lv dd (6)(10) tsec2_txd[4]/ gpout[12] ah23 olv dd (6)(10)(38 ) tsec2_txd[5:7]/ gpout[13:15] ah21, ag22, ag21 o lv dd (6)(10) tsec2_tx_en ab21 olv dd (36) tsec2_tx_er ab19 olv dd (6)(38) tsec2_tx_clk ac21 ilv dd (40) tsec2_gtx_clk ad20 olv dd tsec2_crs ae20 i/o lv dd (37) tsec2_col ae21 ilv dd tsec2_rxd[0:7]/ gpin[8:15] al22, ak22, am21, ah20, ag20, af20, af23, af22 i lv dd (10) tsec2_rx_dv ac19 ilv dd tsec2_rx_er ad21 ilv dd tsec2_rx_clk am22 ilv dd (40) etsec port 3 signals (5) tsec3_txd[0:3] al21, aj21, am20, aj20 o tv dd (6) tsec3_txd[4]/ am19 otv dd tsec3_txd[5:7] ak21, al20, al19 o tv dd (6) tsec3_tx_en ah19 otv dd (36) tsec3_tx_er ah17 otv dd tsec3_tx_clk ah18 itv dd (40) tsec3_gtx_clk ag19 otv dd tsec3_crs ae15 i/o tv dd (37) tsec3_col af15 itv dd tsec3_rxd[0:7] aj17, ae16, ah16, ah14, aj19, ah15, ag16, ae19 i tv dd tsec3_rx_dv ag15 itv dd tsec3_rx_er af16 itv dd tsec3_rx_clk aj18 itv dd (40) etsec port 4 signals (5) tsec4_txd[0:3] ac18, ac16, ad18, ad17 o tv dd (6) tsec4_txd[4] ad16 otv dd (25) tsec4_txd[5:7] ab18, ab17, ab16 o tv dd (6) tsec4_tx_en af17 otv dd (36) tsec4_tx_er af19 otv dd tsec4_tx_clk af18 itv dd (40) tsec4_gtx_clk ag17 otv dd (41) table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
79 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] tsec4_crs ab14 i/o tv dd (37) tsec4_col ac13 itv dd tsec4_rxd[0:7] ag14, ad13, af13, ad14, ae14, ab15, ac14, ae17 i tv dd tsec4_rx_dv ac15 itv dd tsec4_rx_er af14 itv dd tsec4_rx_clk ag13 itv dd (40) local bus signals (5) lad[0:31] a30, e29, c29, d28, d29, h25, b29, a29, c28, l22, m22, a28, c27, h26, g26, b27, b26, a27, e27, g25, d26, e26, g24, f27, a26, a25, c25, h23, k22, d25, f25, h22 i/o ov dd (6) ldp[0:3] a24, e24, c24, b24 i/o ov dd (6)(22) la[27:31] j21, k21, g22, f24, g21 o ov dd (6)(22) lcs [0:4] a22, c22, d23, e22, a23 o ov dd (7) lcs [5]/dma_dreq [2] b23 oov dd (7)(9)(10) lcs [6]/dma_dack [2] e23 oov dd (7)(10) lcs [7]/dma_ddone [2] f23 o ov dd (7)(10) lwe [0:3]/ lsddqm[0:3]/ lbs [0:3] e21, f21, d22, e20 o ov dd (6) lbctl d21 o ov dd lale e19 o ov dd lgpl0/lsda10 f20 o ov dd (25) lgpl1/lsdwe h20 o ov dd (25) lgpl2/loe / lsdras j20 o ov dd lgpl3/lsdcas k20 o ov dd (6) lgpl4/lgta / lupwait/lpbse l21 i/o ov dd (42) lgpl5 j19 o ov dd (6) lcke h19 o ov dd lclk[0:2] g19, l19, m20 o ov dd lsync_in m19 i ov dd lsync_out d20 o ov dd dma signals (5) dma_dreq [0:1] e31, e32 iov dd dma_dreq [2]/lcs [5] b23 i ov dd (9)(10) dma_dreq [3]/irq[9] b30 i ov dd (10) dma_dack [0:1] d32, f30 o ov dd dma_dack[2] /lcs [6] e23 o ov dd (10) dma_dack[3] /irq[10] c30 o ov dd (9)(10) table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
80 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 dma_ddone [0:1] f31, f32 o ov dd dma_ddone [2]/lcs[7] f23 o ov dd (10) dma_ddone [3]/irq[11] d30 o ov dd (9)(10) programmable interrupt controller signals (5) mcp_0 f17 iov dd mcp_1 h17 iov dd (12) s4 irq[0:8] g28, g29, h27, j23, m23, j27, f28, j24, l23 i ov dd irq[9]/dma_dreq[3] b30 iov dd (10) irq[10]/dma_dack[3] c30 iov dd (9)(10) irq[11]/dma_ddone[3] d30 iov dd (9)(10) irq_out j26 oov dd (7)(11) duart signals (5) uart_sin[0:1] b32, c32 iov dd uart_sout[0:1] d31, a32 oov dd uart_cts [0:1] a31, b31 iov dd uart_rts [0:1] c31, e30 oov dd i 2 c signals iic1_sda a16 i/o ov dd (7)(11) iic1_scl b17 i/o ov dd (7)(11) iic2_sda a21 i/o ov dd (7)(11) iic2_scl b21 i/o ov dd (7)(11) system control signals (5) hreset b18 iov dd hreset_req k18 oov dd smi_0 l15 iov dd smi_1 l16 iov dd (12) s4 sreset_0 c20 iov dd sreset_1 c21 iov dd (12) s4 ckstp_in l18 iov dd ckstp_out l17 oov dd (7)(11) ready/trig_out j13 oov dd (10)(25) debug signals (5) trig_in j14 iov dd trig_out/ready j13 oov dd (10)(25) d1_msrcid[0:1]/ lb_srcid[0:1] f15, k15 oov dd (6)(10) d1_msrcid[2]/ lb_srcid[2] k14 oov dd (10)(25) table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
81 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] d1_msrcid[3:4]/ lb_srcid[3:4] h15, g15 oov dd (10) d2_msrcid[0:4] e16, c17, f16, h16, k16 o ov dd d1_mdval/lb_dval j16 oov dd (10) d2_mdval d19 oov dd power management signals (5) asleep c19 oov dd system clocking signals (5) sysclk g16 iov dd rtc k17 iov dd (32) clk_out b16 oov dd (23) test signals (5) lssd_mode c18 iov dd (26) test_mode[0:3] c16, e17, d18, d16 i ov dd (26) jtag signals (5) tck h18 iov dd tdi j18 iov dd (24) tdo g18 oov dd (23) tms f18 iov dd (24) trst a17 iov dd (24) miscellaneous spare j17 ?? (13) gpout[0:7]/ tsec1_txd[0:7] af25, ac23, ag24, ag23, ae24, ae23, ae22, ad22 o ov dd (6)(10) gpin[0:7]/ tsec1_rxd[0:7] al25, al24, ak26, ak25, am26, af26, ah24, ag25 i ov dd (10) gpout[8:15]/ tsec2_txd[0:7] ab20, aj23, aj22, ad19, ah23, ah21, ag22, ag21 o ov dd (10) gpin[8:15]/ tsec2_rxd[0:7] al22, ak22, am21, ah20, ag20, af20, af23, af22 i ov dd (10) additional analog signals temp_anode aa11 thermal ? temp_cathode y11 thermal ? sense, power and gnd signals sensev dd _core0 m14 v dd _core0 sensing pin (31) sensev dd _core1 u20 v dd _core1 sensing pin (12)(31) s1 sensev ss _core0 p14 core0 gnd sensing pin (31) table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
82 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 sensev ss _core1 v20 core1 gnd sensing pin (12)(31) s3 sensev dd _plat n18 v dd _plat sensing pin (28) sensev ss _plat p18 platform gnd sensing pin (29) d1_gv dd b11, b14, d10, d13, f9, f12, h8, h11, h14, k10, k13, l8, p8, r6, u8, v6, w10, y8, aa6, ab10, ac8, ad12, ae10, af8, ag12, ah10, aj8, aj14, ak12, al10, al16 sdram 1 i/o supply d1_gv dd 2.5 - ddr 1.8 ddr2 d2_gv dd b2, b5, b8, d4, d7, e2, f6, g4, h2, j6, k4, l2, m6, n4, p2, t4, u2, w4, y2, ab4, ac2, ad6, ae4, af2, ag6, ah4, aj2, ak6, al4, am2 sdram 2 i/o supply d2_gv dd 2.5v - ddr 1.8v - ddr2 ov dd b22, b25, b28, d17, d24, d27, f19, f22, f26, f29, g17, h21, h24, k19, k23, m21, am30 duart, local bus, dma, multiprocessor interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, jtag and miscellaneous i/o voltage ov dd 3.3v lv dd ac20, ad23, ah22 tsec1 and tsec2 i/o voltage lv dd 2.5/3.3v tv dd ac17, ag18, ak20 tsec3 and tsec4 i/o voltage tv dd 2.5/3.3v sv dd h31, j29, k28, k32, l30, m28, m31, n29, r30, t31, u29, v32, w30, y31, aa29, ab32, ac30, ad31, ae29, ag30, ah31, aj29, ak32, al30, am31 transceiver power supply serdes sv dd 1.05/1.1v xv dd _ srds1 k26, l24, m27, n25, p26, r24, r28, t27, u25, v26 serial i/o power supply for serdes port 1 xv dd _ srds1 1.05/1.1v xv dd _ srds2 aa25, ab28, ac26, ad27, ae25, af28, ah27, ak28, am27, w24, y27 serial i/o power supply for serdes port 2 xv dd _ srds2 1.05/1.1v v dd _core0 l12, l13, l14, m13, m15, n12, n14, p11, p13, p15, r12, r14, t11, t13, t15, u12, u14, v11, v13, v15, w12, w14, y12, y13, y15, aa12, aa14, ab13 core 0 voltage supply v dd _core0 1.05/1.1v v dd _core1 r16, r18, r20, t17, t19, t21, t23, u16, u18, u22, v17, v19, v21, v23, w16, w18, w20, w22, y17, y19, y21, y23, aa16, aa18, aa20, aa22, ab23, ac24 core 1 voltage supply v dd _core1 1.05/1.1v (12) s1 v dd _plat m16, m17, m18, n16, n20, n22, p17, p19, p21, p23, r22 platform supply voltage v dd _plat 1.05/1.1v av dd _core0 b20 core 0 pll supply av dd _core0 1.05/1.1v av dd _core1 a19 core 1 pll supply av dd _core1 1.05/1.1v (12) s2 table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
83 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] av dd _plat b19 platform pll supply voltage av dd _plat 1.05/1.1v av dd _lb a20 local bus pll supply voltage av dd _lb 1.05/1.1v av dd _srds1 p32 serdes port 1 pll & dll power supply av dd _srds1 1.05/1.1v av dd _srds2 af32 serdes port 2 pll & dll power supply av dd _srds2 1.05/1.1v gnd c3, c6, c9, c12, c15, c23, c26, e5, e8, e11, e14, e18, e25, e28, f3, g7, g10, g13, g20, g23, g27, g30, h5, j3, j9, j12, j15, j22, j25, k7, l5, l20, m3, m9, m12, n7, n11, n13, n15, n17, n19, n21, n23, p5, p12, p16, p20, p22, r3, r9, r11, r13, r15, r17, r19, r21, r23, t7, t12, t14, t16, t18, t20, t22, u5, u11,u13, u15, u17, u19, u21, u23, v3, v9, v12, v14, v16, v18, v22, w7, w11, w13, w15, w17, w19, w21, w23,y5, y14, y16, y18, y20, y22, aa3, aa9, aa13, aa15, aa17, aa19, aa21, aa23, ab7, ab24, ac5, ac11, ad3, ad9, ad15, ae7, ae13, ae18, af5, af11, af21, af24, ag3, ag9, ah7, ah13, aj5, aj11, ak3, ak9, ak15, ak19, ak23, al7, al13 gnd ? agnd_srds1 p30 serdes port 1 ground pin for av dd _srds1 ? agnd_srds2 af30 serdes port 2 ground pin for av dd _srds2 ? sgnd h28, h32, j30, k31, l28, l29, m32, n30, r29, t32, u30, v31, w29,y32 aa30, ab31, ac29, ad32, ae30, ag29, ah32, aj30, ak31, al29, am32 ground pins for sv dd xgnd k27, l25, m26, n24, p27, r25, t26, u24, v27, w25, y28, aa24, ab27, ac25, ad28, ae26, af27, ah28, aj26, ak27, al26, am28 ground pins for xv dd _srds n reset configuration signals (20) tsec1_txd[0]/ cfg_alt_boot_vec af25 ?lv dd tsec1_txd[1]/ cfg_platform_freq ac23 ?lv dd (21) tsec1_txd[2:4]/ cfg_device_id[5:7] ag24, ag23, ae24 ? lv dd tsec1_txd[5]/ cfg_tsec1_reduce ae23 ?lv dd tsec1_txd[6:7]/ cfg_tsec1_prtcl[0:1] ae22, ad22 ? lv dd tsec2_txd[0:3]/ cfg_rom_loc[0:3] ab20, aj23, aj22, ad19 ? lv dd tsec2_txd[4], tsec2_tx_er/ cfg_dram_type[0:1] ah23, ab19 ? lv dd (38) tsec2_txd[5]/ cfg_tsec2_reduce ah21 ?lv dd table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
84 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 notes: 1. multi-pin signals such as d1_mdq[0:63] and d2_mdq[0:63] have their physical package pin numbers listed in order corre- sponding to the signal names. 2. stub series terminated logic (sstl-18 and sstl-25) type pins. 3. if a ddr port is not used, it is possible to leave the related power supply (dn_gv dd , dn_mv ref ) turned off at reset. note that these power supplies can only be powered up again at reset for functionality to occur on the ddr port. 4. low voltage differential signaling (lvds) type pins. 5. low voltage transistor-transistor logic (lvttl) type pins. 6. this pin is a reset configuration pin and appears again in th e reset configuration signals section of this table. see the reset configuration signals section of this table for config name and connection details. 7. recommend a weak pull-up resistor (2?10 k ) be placed from this pin to its power supply. 8. recommend a weak pull-down resistor (2?10 k ) be placed from this pin to ground. tsec2_txd[6:7]/ cfg_tsec2_prtcl[0:1] ag22, ag21 ? lv dd tsec3_txd[0:1]/ cfg_spare[0:1] al21, aj21 o tv dd (33) tsec3_txd[2]/ cfg_core1_enable am20 otv dd tsec3_txd[3]/ cfg_core1_lm_offset aj20 ?lv dd tsec3_txd[5]/ cfg_tsec3_reduce ak21 ?lv dd tsec3_txd[6:7]/ cfg_tsec3_prtcl[0:1] al20, al19 ? lv dd tsec4_txd[0:3]/ cfg_io_ports[0:3] ac18, ac16, ad18, ad17 ? lv dd tsec4_txd[5]/ cfg_tsec4_reduce ab18 ?lv dd tsec4_txd[6:7]/ cfg_tsec4_prtcl[0:1] ab17, ab16 ? lv dd lad[0:31]/ cfg_gpporcr[0:31] a30, e29, c29, d28, d29, h25, b29, a29, c28, l22, m22, a28, c27, h26, g26, b27, b26, a27, e27, g25, d26, e26, g24, f27, a26, a25, c25, h23, k22, d25, f25, h22 ?ov dd lwe[0] / cfg_cpu_boot e21 ?ov dd lwe[1] /cfg_rio_sys_size f21 ?ov dd lwe[2:3] / cfg_host_agt[0:1] d22, e20 ?ov dd ldp[0:3], la[27]/ cfg_core_pll[0:4] a24, e24, c24, b24, j21 ? ov dd (22) la[28:31]/ cfg_sys_pll[0:3] k21, g22, f24, g21 ? ov dd (22) lgpl[3], lgpl[5]/ cfg_boot_seq[0:1] k20, j19 ?ov dd d1_msrcid[0]/ cfg_mem_debug f15 ?ov dd d1_msrcid[1]/ cfg_ddr_debug k15 ?ov dd table 18-1. pc8641 signal reference by functional block (continued) name (1) package pin number pin type power supply notes
85 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 9. this multiplexed pin has input stat us in one mode and output in another. 10. this pin is a multiplexed signal for different function al blocks and appears more than once in this table. 11. this pin is open drain signal. 12. functional only on the pc8641d. 13. these pins should be left floating. 14. these pins should be connected to sv dd . 15. these pins should be pulled to ground with a strong resistor (270- to 330- ). 16. these pins should be connected to ov dd . 17. this is a serdes pll/dll digital test signal and is only for factory use. 18. this is a serdes pll/dll analog test signal and is only for factory use. 19. this pin should be pulled to ground with a 100 resistor. 20. the pins in this section are reset configuration pins. each pin has a weak internal pull-up p-fet which is enabled only when the processor is in the reset state. this pull-up is design ed such that it can be overpowered by an external 4.7-k pull-down resistor. however, if the signal is intended to be high after re set, and if there is any device on the net which might pull dow n the value of the net at reset, then a pullup or active driver is needed. 21. should be pulled down at reset if platform frequency is at 400 mhz. 22. these pins require 4.7-k pull-up or pull-down resistors and must be driven as they are used to determine pll configuration ratios at reset. 23. this output is actively driven during reset rather than being tri-stated during reset. 24. hese jtag pins have weak internal pull-up p-fets that are always enabled. 25. this pin should not be pulled down (or driven low) during reset. 26. these are test signals for factory use only and must be pulled up (100 to 1 k .) to ov dd for normal machine operation. 27. dn_mdic[0] should be connected to ground with an 18 resistor 1 and dn_mdic[1] should be connected dn_gv dd . 28. pin n18 is recommended as a reference point for determining the voltage of v dd _plat and is hence considered as the v dd _plat sensing voltage and is called sensev dd _plat. 29. pin p18 is recommended as the ground reference point for sensev dd _plat and is called sensevss_plat. 30. this pin should be pulled to ground with a 200 resistor. 31. these pins are connected to the power/ ground planes internally and may be used by the core power supply to improve tracking and regulation. 32. must be tied low if unused. 33. these pins may be used as defined function al reset configuration pins in the future. please include a resistor pull up/down option to allow flexibility of future designs. 34. used as serial data output for srio 1x/4x link. 35. used as serial data input for srio 1x/4x link. 36. this pin requires an external 4.7 k pull-down resistor to prevent phy from seei ng a valid transmit enable before it is actively driven. 37. this pin is only an output in fifo mode when used as rx flow control. 38. this pin functions as cfg_dram_type[0 or 1] at reset and must be valid before hreset assertion in device sleep mode. 39. should be pulled to ground if unused (such as in fifo, mii and rmii modes). 40. see section 19.4.2 ?platform to fi fo restrictions? on page 89 for clock speed limitations for this pin when used in fifo mode. 41. the phase between the output clocks tsec1_gtx_clk and t sec2_gtx_clk (ports 1 and 2) is no more than 100 ps. the phase between the output clocks t sec3_gtx_clk and tsec4_gtx_clk (ports 3 and 4) is no more than 100 ps. 42. for systems which boot from local bus (gpcm)-controlled flash, a pullup on lgpl4 is required.
86 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 special notes for single core device: s1. solder ball for this signal will not be populated in the single core package. s2. the pll filter from v dd _core1 to av dd _core1 should be removed. av dd _core1 should be pulled to ground with a weak (2?10 k ) resistor. see section 21.2.1 ?pll power s upply filtering? on page 96 for more details. s3. this pin should be pulled to gnd for the single core device. s4. no special requirement for this pin on single core device. pin should be tied to power supply as directed for dual core. 19. clocking this section describes the pll configuration of the pc8641. note that the platform clock is identical to the mpx clock. 19.1 clock ranges table 19-1 provides the clocking specifications for the processor cores and table 19-2 provides the clocking specifications for the memory bus. notes: 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chos en such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock freq uency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2 ?mpx to sysclk pll ratio? on page 87 and section 19.3 ?e600 to mpx clock pll ratio? on page 88 , for ratio settings. 2. the minimum e600 core frequency is based on the minimum platform clock frequency of 400 mhz. notes: 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chos en such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock freq uency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2 ?mpx to sysclk pll ratio? on page 87 . 2. the memory bus clock speed is half the ddr/ddr2 data rate, hence, half the mpx clock frequency. table 19-1. processor core clocking specifications characteristic maximum processor core frequency unit notes 1000 mhz 1250 mhz 1333 mhz 1500 mhz min max min max min max min max e500 core processor frequency 800 1000 800 1250 800 1333 800 1500 mhz (1)(2) table 19-2. memory bus clocking specifications characteristic maximum processor core frequency unit notes 1000, 1250, 1333, 1500 mhz min max memory bus clock frequency 200 300 mhz (1)(2)
87 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] notes: 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chos en such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock freq uency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2 ?mpx to sysclk pll ratio? on page 87 and section 19.3 ?e600 to mpx clock pll ratio? on page 88 for ratio settings. 2. platform/mpx frequencies between 400 and 500 mhz are not supported. note: 1. the local bus clock speed on lclk[0:2] is determined by mpx clock divided by the local bus pll ratio programmed in lccr[clkdiv]. see the reference manual for the pc8641d for more information on this. 19.2 mpx to sysclk pll ratio the mpx clock is the clock that driv es the mpx bus, and is also called the platform clock. the frequency of the mpx is set using the following reset signals, as shown in table 19-5 : ? sysclk input signal ? binary value on la[28:31] at power up note that there is no default for this pll ratio; th ese signals must be pulled to the desired values. also note that the ddr data rate is the determining factor in selecting the mpx bus frequency, since the mpx frequency must equal the ddr data rate. table 19-3. platform/mpx bus clock ing specifications characteristic maximum processor core frequency unit notes 1000, 1250, 1333, 1500 mhz min max platform/mpx bus clock frequency 400 500-600 mhz (1)(2) table 19-4. local bus clocking specifications characteristic maximum processor core frequency unit notes 1000, 1250, 1333, 1500 mhz min max local bus clock speed (for local bus controller) 25 133 mhz (1) table 19-5. mpx:sysclk ratio binary value of la[28:31] signals mpx:sysclk ratio 0000 reserved 0001 reserved 0010 2:1 0011 3:1 0100 4:1 0101 5:1 0110 6:1 0111 reserved 1000 8:1 1001 9:1
88 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 19.3 e600 to mpx clock pll ratio table 19-6 describes the clock ratio between the platform and the e600 core clock. this ratio is deter- mined by the binary value of ldp[0:3], la[27](cfg_c ore_pll[0:4] - reset config name) at power up, as shown in table 19-6 . 19.4 frequency options 19.4.1 sysclk to platform frequency options table 19-7 shows some sysclk frequencies and the ex pected mpx frequency values based on the mpx clock to sysclk ratio. note that frequenc ies between 400 mhz and 500 mhz are not supported on the platform. see note regarding cfg_platform_freq in section 18. ?signal listings? on page 75 since it is a reset configuration pin that is related to platform frequency. note: 1. sysclk frequency range is 66-168 mhz. platfo rm clock/ mpx frequency range is 400 mhz, 500- 600 mhz. table 19-6. e600 core to mpx clock ratio binary value of ldp[0:3], la[27] signals e600 core:mpx clock ratio 01000 2:1 01100 2.5:1 10000 3:1 11100 3.5:1 10100 4:1 01110 4.5:1 table 19-7. frequency options of sysclk with re spect to platform/mpx clock speed mpx to sysclk ratio sysclk (mhz) 66 83 100 111 133 167 platform/mpx frequency (mhz) (1) 2 3 400 500 4 400 533 5 500 555 6 400 500 600 8 533 9 600
89 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 19.4.2 platform to fifo restrictions please note the following fifo maximum speed restrictions based on platform speed. for fifo gmii mode: fifo tx/rx clock frequency <= platform clock frequency / 4.2 for example, if the platform frequency is 533mhz, the fifo tx/rx clock frequency should be no more than 127 mhz for fifo encoded mode: fifo tx/rx clock frequency <= platform clock frequency / 3.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no more than 167 mhz 20. thermal this section describes the thermal specifications of the pc8641. 20.1 thermal characteristics table 20-1 provides the package thermal characteristics for the pc8641. notes: 1. junction temperature is a function of die size , on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temper ature, air flow, power dissipation of other compo- nents on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single-layer board (jesd51-3) horizontal. 3. per jedec jesd51-6 with the board (jesd51-7) horizontal. 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temper- ature is measured on the top surf ace of the board near the package. 5. this is the thermal resistance between die and case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the calculated case temperature. actual thermal resistance is less than 0.1 c/w. note: the thermal performance of the lga and the bga ve rsions of the package are the same. for the thermal model, the only difference is the height of the solder layer under the substrate. table 20-1. package thermal characteristics characteristic symbol value unit notes junction-to-ambient thermal resistance, natural convection, single-layer (1s) board r ja 18 c/w (1)(2) junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board r ja 13 c/w (1)(3) junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board r jma 13 c/w (1)(3) junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board r jma 9 c/w (1)(3) junction-to-board thermal resistance r jb 5 c/w (4) junction-to-case th ermal resistance r jc < 0.1 c/w (5)
90 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 20.2 thermal management information this section provides thermal management information for the high coefficient of thermal expansion (hitce) package for air-cooled applications. proper thermal control design is pr imarily dependent on the system-level design: the heat sink, airflow, and t hermal interface material. the pc8641 implements sev- eral features designed to assist with thermal management, including the temperature diode. the temperature diode allows an external device to moni tor the die temperature in order to detect excessive temperature conditions and alert the system; see section 20.2.4 ?temperature diode? on page 94 , for more information. to reduce the die-junction temperature, heat sinks are required; due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. in any implementation of a heat sink solution, the force on the die should not exceed ten pounds force (45 newtons). figure 20-1 and fig- ure 20-2 on page 91 show a spring clip through the board. occasionally the spring clip is attached to soldered hooks or to a plastic backing structure. screw and spring arrangements are also frequently used. figure 20-1. fc-cbga package exploded cro ss-sectional view with se veral heat sink options a clip-on-chip heat sink solution will not work with the fc-clga part. a through-hole solution is recommended, as shown in figure 20-2 on page 91 below. hcte fc-cbga package heat sink heat sink clip thermal interface material printed-circuit board
91 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 20-2. fc-clga package exploded cross-sectional view with several heat sink options ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal per- formance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 20.2.1 internal package conduction resistance for the exposed-die packaging technology described in table 20-1 on page 89 , the intrinsic conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance (the case is actua lly the top of the exposed silicon die) ? the die junction-to-board thermal resistance figure 20-3 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. figure 20-3. package with heat sink mounted to a printed-circuit board heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced- air convection. because the silicon thermal resistance is quite smal l, the temperature drop in the silicon may be neglected for a first-order analysis. thus the thermal interface material and the heat sink conduction/con- vective thermal resistances are the dominant terms. hcte fc-clga package heat sink clip heat sink thermal interface material printed-circuit board external resistance external resistance internal resistance radiation convection heat sink thermal interface material die/package die junction package/leads printed-circuit board radiation convection
92 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 20.2.2 thermal inte rface materials a thermal interface material is recommended at the pa ckage-to-heat sink interface to minimize the ther- mal contact resistance. figure 20-4 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/o il, fluoroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resis- tance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 20-1 on page 90 ). therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended due to the high power dissipation of the pc8641. of course, the selection of any thermal interface material depends on many factors?thermal performance r equirements, manufacturab ility, service temperatur e, dielectric properti es, cost, and so on. figure 20-4. thermal performance of select thermal interface materials 20.2.3 heat sink selection example the following section provides a heat sink selecti on example using one of the commercially available heat sinks. for preliminary heat sink sizing, the die-junc tion temperature can be expressed as follows: t j = t i + t r + (r jc + r int + r sa ) p d where t j is the die-junction temperature 0 0.5 1 1.5 2 010 20304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
93 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet r jc is the junction-to-case thermal resistance r int is the adhesive or interface material thermal resistance r sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation, the die-junction temperatures ( t j ) should be maintained less than the value specified in table 3-2 on page 7 . the temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise withi n the electronic cabinet. an electronic cabinet inlet- air temperature ( t i ) may range from 30 to 40 c. the air temperature rise within a cabinet ( t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material (r int ) is typically about 0.2 c/w. for example, assuming a t i of 30 c, a t r of 5 c, a package r jc = 0.1, and a typical power consumption (p d ) of 43.4 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 0.2 c/w + sa ) 43.4 w for this example, a r sa value of 1.32 c/w or less is required to maintain the die junction temperature below the maximum value of table 3-2 . though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common fig- ure-of-merit used for comparing the thermal per formance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal manage- ment because no single parameter can adequately descr ibe three-dimensional heat flow. the final die- junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature?airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on. due to the complexity and variety of system-level bo undary conditions for toda y's microelectronic equip- ment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs. for system thermal modeling, the pc8641 thermal model is shown in figure 20-5 on page 94 . four cuboids are used to represent this device. the die is modeled as 12.4x15.3 mm at a thickness of 0.86 mm. see section 4. ?power characteristics? on page 12 for power dissipation details. the substrate is modeled as a single block 33x33x1.2 mm with orthotro pic conductivity: 13.5 w/(m ? k) in the xy-plane and 5.3 w/(m ? k) in the z-direction. the die is centered on the substrate. the bump/underfill layer is modeled as a collapsed thermal resistance between the die and substrate with a conductivity of 5.3 w/(m ? k) in the thickness dimens ion of 0.07 mm. because the bump/u nderfill is modeled with zero phys- ical dimension (collapsed height), the die thickness was slightly enlarged to provide the correct height. the c5 solder layer is modeled as a cuboid with dimensions 33x33x0.4 mm and orthotropic thermal con- ductivity of 0.034 w/(m ? k) in the xy-plane and 9.6 w/(m ? k) in the z-direction. an lga solder layer would be modeled as a collapsed thermal resistance with thermal conductivity of 9.6w/(m ? k) and an effective height of 0.1 mm. the thermal model uses approximate dimensions to reduce grid. please refer to the case outline for actual dimensions.
94 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 20-5. recommended thermal model of pc8641 20.2.4 temperature diode the pc8641 has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as analog devices, adt7461 ? ). these devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. for proper operation, the monitoring device used should auto-calibrate the device by canceling out the v be variation of each pc8641?s internal diode. the following are the specifications of the pc8641 on-board temperature diode: vf > 0.40v vf < 0.90v operating range 2-300 a diode leakage < 10 na at 125 c ideality factor over 5-150 a at 60 c: n = 1.0275 0.9% ideality factor is defined as the deviation from the ideal diode equation: bump and underfill die substrate c5 solder layer die substrate side view of model (not to scale) top view of model (not to scale) x y z conductivity value unit die (12.4 x 15.3 x 0.86 mm) silicon temperature dependent bump and underfill (12.4 x 15.3 x 0.07 mm) collapsed resistance k z 5.3 substrate (33 x 33 x 1.2 mm) k x 13.5 k y 13.5 k z 5.3 c5 solder layer (33 x 33 x 0.4 mm) k x 0.034 k y 0.034 k z 9.6 w/(m x k) w/(m x k) w/(m x k) i fw i s e qv f nkt ---------- - 1 ? =
95 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] another useful equation is: where: i fw = forward current i s = saturation current v d = voltage at diode v f = voltage forward biased v h = diode voltage while i h is flowing v l = diode voltage while i l is flowing i h = larger diode bias current i l = smaller diode bias current q = charge of electron (1.6 x 10 -19 c) n = ideality factor (normally 1.0) k = boltzman?s constant (1.38 x 10 -23 joules/k) t = temperature (kelvins) the ratio of i h to i l is usually selected to be 10:1. the above simplifies to the following: v h ? v l = 1.986 10 -4 nt solving for t, the equation becomes: 21. system design information this section provides electrical and thermal design recommendations fo r successful application of the pc8641. 21.1 system clocking this device includes six plls, as follows: 1. the platform pll generates th e platform clock from the exte rnally supplied sysclk input. the frequency ratio between the platform and sysclk is selected using the platform pll ratio con- figuration bits as described in section 19.2 ?mpx to sysclk pll ratio? on page 87 . 2. the dual e600 core plls generate the e600 clock from the externally supplied input. 3. the local bus pll generates the clock for the local bus. 4. there are two internal plls for the serdes block. v h v l ? n kt q ------- i i h i l ----- = nt v h v l ? 1.986 10 4 ? --------------------------------- - =
96 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 21.2 power supply d esign and sequencing 21.2.1 pll power supply filtering each of the plls listed above is provided wit h power through independent power supply pins. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide independent filter circuits per pll power supply as illustrated in figure 21-2 , one to each of the av dd type pins. by providing independent filters to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the pl ls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacit ors with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple sm all capacitors of equal value are recommended over a single large value capacitor. each circuit should be pl aced as close as possibl e to the specific av dd type pin being supplied to mini- mize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd type pin, which is on the periphery of the footprint, without the inductance of vias. figure 21-1 and figure 21-2 show the pll power supply filter circuits for the platform and cores, respectively. figure 21-1. pc8641 pll power supply filter circuit (for platform and local bus) figure 21-2. pc8641 pll power supply filter circuit (for cores) note: for single core device the filter circuit (in the dashed box) should be removed and av dd _core1 should be tied to ground with a weak (2-10 k ) pull-down resistor. the av dd _srdsn signals provide power for the analog portions of the serdes pll. to ensure stability of the internal clock, the power supplied to the pll is filtered using a circuit similar to the one shown in following figure. for maximum effectiveness, the filter circuit is placed as cl osely as possible to the av dd _srdsn balls to ensure it filters out as much noise as possible. the ground connection should be near the av dd _srdsn balls. the 0.003-f capacitor is closes t to the balls, followed by the 1-f capaci- tor, and finally the 1 ohm resistor to the board supply plane. the capacitors are connected from av dd _srdsn to the ground plane. use ceramic chip capacitors with the hi ghest possible self-resonant frequency. all traces should be kept short, wide and direct. 2. 2 f 2. 2 f gnd 10 v dd _plat av dd _plat, av dd _lb low esl surface mount capacitors v dd _core0/1 a v dd _core0/1 2.2 f 2.2 f gnd low esl surface mount capacitors 10 filter circuit (should not be used for single core device)
97 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 21-3. serdes pll power supply filter note: 1. an 0805 sized capacitor is reco mmended for system initial bring-up. note the following: ?av dd should be a filtered version of sv dd . ? signals on the serdes interface are fed from the sv dd power plan. 21.2.2 pll power supply sequencing for details on power sequencing for the av dd type and supplies refer to section 3.2 ?power up/down sequence? on page 10 21.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the pc8641 system, and the device itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each ov dd , dn_gv dd , lv dd , tv dd , v dd _core n , and v dd _plat pin of the device. these decoupling capacitors should receive their power from separate ov dd , dn_gv dd , lv dd , tv dd , v dd _core n , and v dd _plat and gnd power planes in the pcb, utilizing short traces to minimize inductanc e. capacitors may be placed directly under the device using a stan- dard escape pattern. others may surround the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the ov dd , dn_gv dd , lv dd , tv dd , v dd _core n , and v dd _plat planes, to enable quick recharg- ing of the smaller chip capacitors. they should also be connected to the power and ground planes through two vias to minimize inductance. sugges ted bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 1.0 f (1) 0.003 f gnd 1.0 avdd_srdsn n = 1, 2 sv dd
98 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 21.4 serdes block power suppl y decoupling recommendations the serdes block requires a clean, tight ly regulated source of power (sv dd and xv dd _srdsn) to ensure low jitter on transmit and reliable recovery of data in the receiver. an appropriate decoupling scheme is outlined below. only surface mount technology (smt) capacitors sh ould be used to minimize inductance. connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. ? first, the board should have at least 10 x 10-nf smt ceramic chip capacitors as close as possible to the supply balls of the device. where the board ha s blind vias, these capacitors should be placed directly below the chip supply and ground connections. where the board does not have blind vias, these capacitors should be placed in a ring aroun d the device as close to the supply and ground connections as possible. ? second, there should be a 1-f ceramic chip capacitor on each side of the device. this should be done for all serdes supplies. ? third, between the device and any serdes voltage regulator there should be a 10-f, low equivalent series resistance (esr) smt tantalum chip capacitor and a 100-f, low esr smt tantalum chip capacitor. this should be done for all serdes supplies. 21.5 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. in general all unused active low inputs should be tied to ov dd , dn_gv dd , lv dd , tv dd , v dd _core n , and v dd _plat, xv dd _srdsn, and sv dd as required and unused active high inputs should be con- nected to gnd. all nc (no-connect) signals must remain unconnected. special cases: ddr - if one of the ddr ports is not being used the power supply pins for that port can be connected to ground so that there is no need to connect the individu al unused inputs of that port to ground. note that these power supplies can only be powered up again at reset for functionality to occur on the ddr port. power supplies for other functional buses should remain powered. local bus - if parity is not used, tie ldp[0:3] to ground via a 4.7 k resistor, tie lpbse to ov dd via a 4.7 k resistor (pull-up resistor). serdes - receiver lanes configured for pci express are allowed to be disconnected (as would occur when a pci express slot is connected but not populat ed). directions for terminating the serdes signals is discussed in section 21.5.1 ?guidelines for high-speed interface termination? on page 98 . 21.5.1 guidelines for high-speed interface termination 21.5.1.1 serdes interface the high-speed serdes interface can be disabled through the por input cfg_io_ports[0:3] and through the devdisr register in software. if a serdes port is disabled through the por input the user can not enable it through the devdisr register in software. however, if a serdes port is enabled through the por input the user can disable it through the devdisr register in software. disabling a serdes port through software should be done on a temporary basis. power is always required for the serdes inter- face, even if the port is disabled through either mechanism. table 21-1 describes the possible enabled/disabled scenarios for a se rdes port. the termination recommendations must be followed for each port.
99 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] notes: 1. partial termination when a serdes port is enabled through both por input and devdisr is deter- mined by the serdes port mode. if the port is in x8 pci express mode, no termination is required because all pins are being used. if the port is in x1/x2/x4 pci express mode, termination is required on the unused pins. if the port is in x4 serial rapidio mode termination is required on the unused pins. 2. if a serdes port is enabled through the por input and then disabled through devdisr, no hardware changes are required. termination of the serdes port should follow what is required when the port is enabled through both por input and devdisr. see note (1) for more information. if the high-speed serdes port requires complete or partial termination, the unused pins should be termi- nated as described in this section. the following pins must be left unconnected (floating): ?sd n _tx[7:0] ?sd n _tx[ 7:0] the following pins must be connected to gnd: ?sd n _rx[7:0] ?sd n _rx [7:0] ?sd n _ref_clk ? sd n _ref_clk note: it is recommended to power down the unused lane through srds1cr1[0:7] register (offset = 0xe_0f08) and srds2cr1[0:7] register (offset = 0xe_0f44.) (thi s prevents the oscillations and holds the receiver output in a fixed state.) that maps to serdes lane 0 to lane 7 accordingly. for other directions on reserv ed or no-connects pins see section 18. ?signal listings? on page 75 . table 21-1. serdes port enabled/disabled configurations disabled through por input enabled through por input enabled through devdisr serdes port is disabled (and cannot be enabled through devdisr) complete termination required (reference clock not required) serdes port is enabled partial termination may be required (1) (reference clock is required) disabled through devdisr serdes port is disabled (through por input) complete termination required (reference clock not required) serdes port is disabled after software disables port same termination requirements as when the port is enabled through por input (2) (reference clock is required)
100 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 21.6 pull-up and pull-dow n resistor requirements the pc8641 requires weak pull-up resistors (2?10 k is recommended) on all open drain type pins. the following pins must not be pulled down during power-on reset: tsec4_txd[4], lgpl0/lsda10, lgpl1/lsdwe , trig_out/ready, and d1_msrcid[2]. the following are factory test pins and require strong pull up resistors (100 ?1 k ) to ov dd lssd_mode , test_mode[0:3].the following pins require weak pull up resistors (2?10 k ) to their specific power supplies: lcs [0:4], lcs [5]/dma_dreq2 , lcs [6]/dma_dack [2], lcs [7]/dma_ddone [2], irq_out, iic1_sda, iic1_scl, iic2_sda, iic2_scl, and ckstp_out . the following pins should be pulled to ground with a 100 resistor: sd1_imp_cal_tx, sd2_imp_cal_tx. the following pins should be pulled to ground with a 200 resistor: sd1_imp_cal_rx, sd2_imp_cal_rx. tsecn_tx_en signals require an external 4.7-k resistor to prevent phy from seeing a valid transmit enable before it is actively driven. when the platform frequency is 400 mhz, tsec1_txd[1] must be pulled down at reset. tsec2_txd[4] and tsec2_tx_er pins function as cfg_dram_type[0 or 1] at reset and must be valid before hreset assertion when co ming out of device sleep mode. 21.6.1 special instructions for single core device the mechanical drawing for the single core device does not have all the solder balls that exist on the sin- gle core device. this includes all the balls for v dd _core1 and sensev dd _core1 which exist on the package for the dual core device, but not on the sing le core package. a solder ball is present for sensev ss _core1 and needs to be connected to ground with a weak (2-10 k ) pull down resistor. like- wise, av dd _core1 needs to be pulled to ground as shown in figure 21-2 on page 96 . the mechanical drawing for the single core device is located in section 17.2 ?mechanical dimensions of the pc8641 fc-cbga? on page 73 . for other pin pull-up or pull-down recommendations of signals, please see section 18. ?signal listings? on page 75 . 21.7 output buffer dc impedance the pc8641 drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 21-4 on page 101 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z0 = (r p + r n )/2.
101 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 21-4. driver impedance measurement table 21-2 summarizes the signal impedance targets. the driver impedances are targeted at minimum v dd , nominal ov dd , 110 c. note: nominal supply voltages. see table 3-1 on page 6 , t j = 110 c 21.8 configurati on pin muxing the pc8641 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treat ed as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal functi on. most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k . this value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. the pull-up resistor is enabled only during hreset (and for platform /sys tem clocks after hreset deassertion to ensure capture of the reset value). when the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. the default value for all configuration bits treated this way has been encoded such that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disrupti on of signal quality or speed for output pins thus configured. the platform pll ratio and e600 pll ratio configuration pins are not equipped with these default pull-up devices. table 21-2. impedance characteristics impedance duart, control, configuration, power management pci express ddr dram symbol unit r n 43 target 25 target 20 target z 0 w r p 43 target 25 target 20 target z 0 w ovdd ognd r p r n pad data sw1 sw2
102 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 21.9 jtag configuration signals correct operation of the jtag interface requires configuration of a group of system control pins as dem- onstrated in figure 21-6 on page 104 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spu- rious assertion will give unpredictable results. boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all processors that implement the power architecture tech- nology. the device requires trst to be asserted during reset conditions to ensure the jtag boundary logic does not interfere with normal chip operation. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop port connects primarily through the jtag interface of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 21-5 on page 103 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. the cop interface has a standard header, shown in figure 21-5 , for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. the cop header adds many benefits such as breakpoi nts, watchpoints, register and memory examina- tion/modification, and other standard debugger featur es. an inexpensive option can be to leave the cop header unpopulated until needed. there is no standardized way to number the cop header shown in figure 21-5 ; consequently, many dif- ferent pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top- to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 21-5 is common to all known emulators. for a multi-processor non-daisy chain configuration, figure 21-6 , can be duplicated for each processor. the recommended daisy chain configuration is shown in figure 21-7 on page 105 . please consult with your tool vendor to determine which configuration is supported by their emulator.
103 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 21.9.1 termination of unusual signals if the jtag interface and cop header will not be used, e2v recommends th e following connections: ?trst should be tied to hreset through a 0 k isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during the power-on reset flow. e2v recommends that the cop header be designed into the system as shown in figure 21-6 on page 104 . if this is not possible, the isolatio n resistor will allow fu ture access to trst in case a jtag interface may need to be wired onto the system in future debug situations. ? tie tck to ov dd through a 10 k resistor. this will prevent tck from changing state and reading incorrect data into the device. ? no connection is required for tdi, tms, or tdo. figure 21-5. cop connector physical pinout 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin 1 2 cop_tdo cop_tdi nc nc cop_trst cop_vdd_sense cop_chkstp_in nc nc gnd cop_tck cop_tms cop_sreset cop_hreset cop_chkstp_out
104 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 figure 21-6. jtag/cop interface connection for one pc8641 device notes: 1. the cop port and target board shou ld be able to independently assert hreset and trst to the pro- cessor in order to fully control the processor as shown here. 2. populate this with a 10 resistor for short-circuit/current-limiting protection. 3. the key location (pin 14) is not ph ysically present on the cop header. 4. although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional gnd pin for improved signal integrity. 5. this switch is included as a precaution for bsdl testing. the switch should be open during bsdl test- ing to avoid accidentally asserting the trst line. if bsdl testing is not being performed, this switch should be closed or removed. hreset from target board sources cop_hreset 13 cop_sreset sreset 1 nc 11 cop_vdd_sense 2 6 5 15 10 10 k 10 k cop_chkstp_in ckstp_in 8 cop_tms cop_tdo cop_tdi cop_tck tms tdo tdi 9 1 3 4 cop_trst 7 16 2 10 12 (if any) cop header 14 3 10 k trst 1 10 k 10 k 10 k ckstp_out cop_chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pinout 1 2 nc srese t1 nc ov dd 10 k 10 k hreset 1 tck 4 5 10 k sreset 0 10 k srese t0
105 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] figure 21-7. jtag/cop interface connection for multiple pc8641 devices in daisy chain configuration notes: 1. populate this with a 10 resistor for short circuit/current-limiting protection. 2. key location; pin 14 is not physic ally present on the cop header. 3. use a and gate with sufficient drive strength to drive two inputs. 4. the cop port and target board should be able to independently assert hreset and trst to the processor in order to fully control the processor as shown above. 5. this switch is included as a precaution for bsdl testing. the switch should be open during bsdl testing to avoid acciden- tally asserting the trst line. if bsdl testing is not being performed, this switch should be closed or removed. 6. although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional gnd pin for improved signal integrity. cop_sreset cop_trst cop_hreset jtag/cop sreset1 sreset0 tdi header hreset trst chkstp_out chkstp_in tms tck tdo 10 k 10 k sreset1 hreset from target board sources (if any) cop_tdi 11 13 3 cop_chkstp_out cop_chkstp_in sreset1 sreset0 tdi trst chkstp_out chkstp_in tms tck tdo 4 15 8 cop_tms 2 10 cop_tck gnd 14 9 7 6 nc nc cop_vdd_sense 16 cop_tdo 1 3 12 2 hreset ov dd sreset0 4 4 4 4 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 6 5 10 pc8641 pc8641 3 5 nc 1 ov dd
106 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 22. ordering information ordering information for the parts fully covered by this specification document is provided in section 22.1 ?part numbers fully addressed by this document? . 22.1 part numbers fully addressed by this document figure 22-1 provides the e2v part numbering nomenclature for the pc8641. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local e2v. in addition to the processor frequency, the part numbering scheme also includes an applica- tion modifier which may specify spec ial application conditions. each part number also contains a revision code which refers to the die mask revision number. figure 22-1. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designates a "prototype" pr oduct that has not been qualified by e2v. reliability of a pcx par t- number is not guaranteed and such part-number shall not be us ed in flight hardware. product changes may still occur while shipping prototypes. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specifica - tion support all core frequencies. additionally, parts address ed by part number specifications may support other maximum core frequencies. 4. part number pc8641xxx1000nx is our low v dd _core n device. v dd _core n = 0.95v and v dd _plat = 1.05v. 23. definitions 23.1 life support applications these products are not designed for use in life s upport appliances, devices or systems where malfunc- tion of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products fo r use in such applications do so at thei r own risk and agree to fully indemnify e2v for any damages resulting from such improper use or sale. xx xx x 8641 part identifier core count ddr speed (mhz) 8641 x blank = single core d = dual core product code (1) pc(x) (2) package (1) revision level (1) gh = hitce fc-cbga sh = rohs hitce fc-cbga nnnn 1000, 1250, 1333, 1500 x revision b = 2.0 system version register value for rev b: 0x80 9 0_0020 - pc8641 0x80 9 0_0120 - pc8641d revision c = 2.1 system version register value for rev c: 0x80 9 0_0021 - pc8641 0x80 9 0_0121 - pc8641d revision e = 3.0 system version register value for rev e: 0x80 9 0_0030 - pc8641 0x80 9 0_0130 - pc8641d core processor frequency (mhz) (3) n = 500 mhz k = 600 mhz j = 533 mhz h = 500 mhz g = 400 mhz (4) y temperature range (1) v: t c = -40?c, t j = +110?c m: t c = -55?c, t j = +125?c
107 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 24. document revision history table 24-1 provides a revision history for this hardware specification. table 24-1. document revision history rev. no date substantive change(s) 0893c 01/2010 - updated table 4-1 on page 12 and table 4-3 on page 14 : added tbc for maximum power consumption at t j = 125c - added note (8) to table 15-2 on page 56 - added revision e to figure 22-1 ?ordering information? on page 106 0893b 12/2008 - added section 5.4 ?platform frequency requi rements for pci-express and serial rapidio? on page 17 - removed the statement ?note that co re processor speed of 1500 mhz is only available for the pc8641d (dual core)? from note 3 in figure 22-1 on page 106 - added figure 17-2 on page 74 and notes - added note 8 to figure 17-1 on page 73 and figure 17-2 on page 74 0893a 04/2008 initial revision.
i 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] table of contents features............... ................. .............. .............. .............. .............. ............. 1 overview.............. ................. .............. .............. .............. .............. ............. 1 screening ............ ................. .............. .............. .............. .............. ............. 1 1 block diagram ........... ................. ................ ................. ................ ............. 2 2 key features ........... ................ ................. ................ ................. ............... 3 3 electrical characteristics ... .............. .............. .............. .............. ............. 5 3.1 overall dc electrical characteristics ..................................................................... 5 3.2 power up/down sequence .................................................................................. 10 4 power characteristics ........ .............. .............. .............. .............. ........... 12 5 input clocks .............. ................. ................ ................. ................ ........... 15 5.1 system clock timing ............................................................................................ 15 5.2 real time clock timing ....................................................................................... 16 5.3 etsec gigabit reference clock timing .............................................................. 16 5.4 platform frequency requirements for pci-express and serial rapidio ............. 17 5.5 other input clocks ................................................................................................ 17 6 reset initialization ............ .............. .............. .............. .............. ........... 17 7 ddr and ddr2 sdram .......... ................. ................ ................. ............. 18 7.1 ddr sdram dc electrical characteristics ......................................................... 18 7.2 ddr sdram ac electrical characteristics ......................................................... 20 8 duart .............. ................ ................. .............. .............. .............. ........... 25 8.1 duart dc electrical characteristics .................................................................. 25 8.2 duart ac electrical specifications .................................................................... 25 9 ethernet: enhanced three- speed ethernet (etsec) mii management ........... ................ ................ ................. .............. ........... 26 9.1 enhanced three-speed ethernet controller (etsec) (10/100/1gb mbps) gmii/mii/tbi/ rgmii/rtbi/rmii electrical characteristics .............................. 26 9.2 fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications ............. 27 10 ethernet management interf ace electrical characte ristics ............... 39 10.1 mii management dc electrical characteristics .................................................. 39 10.2 mii management ac electrical specifications .................................................... 39
ii 0893c?hirel?01/10 pc8641 and pc8641d [preliminary] e2v semiconductors sas 2010 11 local bus ............... .............. .............. .............. .............. .............. ........... 41 11.1 local bus dc electrical characteristics ............................................................. 41 11.2 local bus ac electrical specifications ............................................................... 41 12 jtag ...................... .............. .............. .............. .............. .............. ........... 50 12.1 jtag dc electrical characteristics .................................................................... 50 13 i 2 c ................. ................. ................ ................ ................. .............. ........... 52 13.1 i 2 c dc electrical characteristics ........................................................................ 52 13.2 i 2 c ac electrical specifications .......................................................................... 53 14 high-speed interf aces ............... ................ ................. ................ ........... 54 14.1 dc requirements for serdes reference clocks ............................................... 54 15 pci express ........... .............. .............. .............. .............. .............. ........... 55 15.1 dc requirements for pci express sd n _ref_clk and sd n _ref_clk ......... 55 15.2 ac requirements for pci express serdes clocks ............................................ 55 15.3 clocking dependencies ...................................................................................... 55 15.4 physical layer specifications ............................................................................. 55 15.5 receiver compliance eye diagrams .................................................................. 60 16 serial rapidio ................ ................ ................. .............. .............. ........... 61 16.1 dc requirements for serial rapidio sd n _ref_clk and sd n _ref_clk ...... 62 16.2 ac requirements for serial rapidio sd n _ref_clk and sd n _ref_clk ...... 62 16.3 signal definitions ................................................................................................ 62 16.4 equalization ........................................................................................................ 63 16.5 explanatory note on transmitter and receiver specifications .......................... 63 16.6 transmitter specifications .................................................................................. 64 16.7 receiver specifications ...................................................................................... 67 16.8 receiver eye diagrams ...................................................................................... 69 16.9 measurement and test requirements ............................................................... 71 17 package .............. ................. .............. .............. .............. .............. ........... 72 17.1 package parameters for the pc8641 ................................................................. 72 17.2 mechanical dimensions of the pc8641 fc-cbga ............................................ 73 18 signal listings ................. ................. .............. .............. .............. ........... 75 19 clocking .............. ................. .............. .............. .............. .............. ........... 86 19.1 clock ranges ..................................................................................................... 86 19.2 mpx to sysclk pll ratio ................ ................ ............. ............. ............ .......... 87
iii 0893c?hirel?01/10 e2v semiconductors sas 2010 pc8641 and pc8641d [preliminary] 19.3 e600 to mpx clock pll ratio ............................................................................. 88 19.4 frequency options ............................................................................................. 88 20 thermal ............. ................ ................. .............. .............. .............. ........... 89 20.1 thermal characteristics ..................................................................................... 89 20.2 thermal management information ..................................................................... 90 21 system design information ... ................. ................ ................. ............. 95 21.1 system clocking ................................................................................................. 95 21.2 power supply design and sequencing .............................................................. 96 21.3 decoupling recommendations .......................................................................... 97 21.4 serdes block power supply decoupling recommendations ............................ 98 21.5 connection recommendations .......................................................................... 98 21.6 pull-up and pull-down resistor requirements ................................................100 21.7 output buffer dc impedance ........................................................................... 100 21.8 configuration pin muxing ................................................................................. 101 21.9 jtag configuration signals .............................................................................102 22 ordering information ............ ................ ................. ................ .............. 106 22.1 part numbers fully addressed by this document ..........................................106 23 definitions ............. ................ ................ ................. ................ .............. 106 23.1 life support applications .................................................................................. 106 24 document revision history .. ............... ................. ................ .............. 107 table of contents ......... ................ ................ ................. ................ ............ i
0893c?hirel?01/10 e2v semiconductors sas 2010 whilst e2v has taken care to ensure the accuracy of the inform ation contained herein it accepts no responsibility for the conse quences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out i n its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. how to reach us home page: www.e2v.com sales offices: europe regional sales office e2v ltd 106 waterhouse lane chelmsford essex cm1 2qu england tel: +44 (0)1245 493493 fax: +44 (0)1245 492492 mailto: enquiries@e2v.com e2v sas 16 burospace f-91572 bivres cedex france tel: +33 (0) 16019 5500 fax: +33 (0) 16019 5529 mailto: enquiries-fr@e2v.com e2v gmbh industriestra?e 29 82194 gr?benzell germany tel: +49 (0) 8142 41057-0 fax: +49 (0) 8142 284547 mailto: enquiries-de@e2v.com americas e2v inc 520 white plains road suite 450 tarrytown, ny 10591 usa tel: +1 (914) 592 6050 or 1-800-342-5338, fax: +1 (914) 592-5148 mailto: enquiries-na@e2v.com asia pacific e2v ltd 11/f., onfem tower, 29 wyndham street, central, hong kong tel: +852 3679 364 8/9 fax: +852 3583 1084 mailto: enquiries-ap@e2v.com product contact: e2v avenue de rochepleine bp 123 - 38521 saint-egrve cedex france tel: +33 (0)4 76 58 30 00 hotline : mailto: std-hotline@e2v.com

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